summaryrefslogtreecommitdiffstats
path: root/target-sparc
Commit message (Expand)AuthorAgeFilesLines
* Fix TCGv size mismatchesblueswir12008-11-011-19/+21
* Add static (spotted by sparse)blueswir12008-10-071-1/+1
* Fix error in fexpand (spotted by sparse)blueswir12008-10-071-4/+4
* Show size for unassigned accesses (Robert Reif)blueswir12008-10-062-14/+15
* Rearrange tick functionsblueswir12008-10-033-31/+31
* Fix missing prototype warnings by moving declarationsblueswir12008-10-032-11/+9
* Fix MXCC printf warning (based on patch by Robert Reif)blueswir12008-10-021-3/+3
* Add mmu tlb demap support (Igor Kovalenko)blueswir12008-09-271-1/+35
* Add a generic Niagara machineblueswir12008-09-262-2/+2
* Implement some UA2007 block ASIsblueswir12008-09-261-0/+6
* Implement UA2005 hypervisor trapsblueswir12008-09-263-18/+23
* Move also DEBUG_PCALL (see r5085)blueswir12008-09-262-1/+1
* Add software and timer interrupt supportblueswir12008-09-224-5/+49
* Fix arguments used in cas/casx, thanks to Igor Kovalenko for spottingblueswir12008-09-221-5/+5
* Use the new concat_tl_i64 op for std and stdablueswir12008-09-211-18/+6
* Use the new concat_i32_i64 op for std and stdablueswir12008-09-213-22/+20
* Move signal handler prototype back to cpu.hblueswir12008-09-202-1/+1
* Fix array subscript above array bounds errorblueswir12008-09-141-1/+1
* Fix mulscc with high bits set in either src1 or src2blueswir12008-09-131-2/+3
* Write zeros to high bits of y, based on patch by Vince Weaverblueswir12008-09-111-2/+4
* Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir12008-09-105-64/+39
* Partially convert float128 conversion ops to TCGblueswir12008-09-103-20/+19
* Convert basic 64 bit VIS ops to TCGblueswir12008-09-104-102/+65
* Convert basic 32 bit VIS ops to TCGblueswir12008-09-103-164/+48
* Convert basic float32 ops to TCGblueswir12008-09-103-190/+329
* Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir12008-09-095-31/+43
* Fix a typo in fpsub32blueswir12008-09-061-1/+1
* Convert most env fields to TCG registersblueswir12008-09-061-95/+91
* Silence gcc warning about constant overflowblueswir12008-09-062-3/+11
* Implement no-fault loadsblueswir12008-09-031-8/+36
* Fix sign extension problems with smul and umul (Vince Weaver)blueswir12008-09-021-4/+4
* Fix y register loads and storesblueswir12008-09-011-18/+16
* Remove memcpy32() prototype leftover from r5109blueswir12008-08-301-1/+0
* Fix FCC handling for Sparc64 target, initial patch by Vince Weaverblueswir12008-08-292-30/+28
* Fix Sparc64 boot on i386 host:blueswir12008-08-295-273/+280
* Fix udiv and sdiv on Sparc64 (Vince Weaver)blueswir12008-08-251-2/+2
* Fix wrwim masking (Luis Pureza)blueswir12008-08-211-0/+3
* Use initial CPU definition structure for some CPU fields instead of copyingblueswir12008-08-214-87/+83
* Correct 32bit carry flag for add instruction (Igor Kovalenko)blueswir12008-08-171-5/+8
* Fix faligndata (Vince Weaver)blueswir12008-08-061-1/+4
* Fix I/D MMU tag readsblueswir12008-08-061-54/+4
* Fix Sparc64 shiftsblueswir12008-08-061-5/+3
* Fix offset handling for ASI loads and stores (Vince Weaver)blueswir12008-08-061-3/+1
* Handle wrapped registers correctly when savingblueswir12008-08-011-1/+11
* Fix cmp/subcc/addcc op bugs reported by Vince Weaverblueswir12008-07-291-4/+4
* Make MAXTL dynamic, bounds check tl when indexingblueswir12008-07-254-51/+56
* Sparc32: save/load all MMU registers, Sparc64: add CPU save/loadblueswir12008-07-242-4/+110
* Add T1 and T2 CPUs, add a Sun4v machineblueswir12008-07-223-1/+26
* Use MMU globals for some MMU trapsblueswir12008-07-212-4/+19
* Fix reset vectorblueswir12008-07-211-1/+1
OpenPOWER on IntegriCloud