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* Fix mulscc with high bits set in either src1 or src2blueswir12008-09-131-2/+3
* Write zeros to high bits of y, based on patch by Vince Weaverblueswir12008-09-111-2/+4
* Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir12008-09-101-35/+16
* Partially convert float128 conversion ops to TCGblueswir12008-09-101-8/+6
* Convert basic 64 bit VIS ops to TCGblueswir12008-09-101-46/+65
* Convert basic 32 bit VIS ops to TCGblueswir12008-09-101-76/+38
* Convert basic float32 ops to TCGblueswir12008-09-101-150/+247
* Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir12008-09-091-8/+23
* Fix a typo in fpsub32blueswir12008-09-061-1/+1
* Convert most env fields to TCG registersblueswir12008-09-061-95/+91
* Silence gcc warning about constant overflowblueswir12008-09-061-2/+2
* Fix sign extension problems with smul and umul (Vince Weaver)blueswir12008-09-021-4/+4
* Fix y register loads and storesblueswir12008-09-011-18/+16
* Fix FCC handling for Sparc64 target, initial patch by Vince Weaverblueswir12008-08-291-4/+2
* Fix wrwim masking (Luis Pureza)blueswir12008-08-211-0/+3
* Use initial CPU definition structure for some CPU fields instead of copyingblueswir12008-08-211-10/+7
* Correct 32bit carry flag for add instruction (Igor Kovalenko)blueswir12008-08-171-5/+8
* Fix Sparc64 shiftsblueswir12008-08-061-5/+3
* Fix offset handling for ASI loads and stores (Vince Weaver)blueswir12008-08-061-3/+1
* Fix cmp/subcc/addcc op bugs reported by Vince Weaverblueswir12008-07-291-4/+4
* Make UA200x features selectable, add MMU typesblueswir12008-07-201-0/+6
* Implement nucleus quad lddablueswir12008-07-191-16/+12
* Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.ths2008-07-181-7/+6
* wrhpr hstick_cmpr is a store, not a loadblueswir12008-07-181-3/+2
* Support for address maskingblueswir12008-07-171-22/+36
* Flushw can generate exceptions, so save PC & NPCblueswir12008-07-161-0/+1
* Really fix casblueswir12008-07-151-6/+5
* Add instruction counter.pbrook2008-06-291-1/+19
* Eliminate cpu_T[0]blueswir12008-06-221-9/+9
* Eliminate cpu_T[1]blueswir12008-06-221-4/+3
* Convert some cpu_dst uses (with loads/stores) to cpu_tmp0blueswir12008-06-211-67/+67
* Avoid brcond problems, use temps for cpu_src1 & cpu_src2blueswir12008-06-211-35/+32
* Avoid temporary variable use across basic blocks for udivxblueswir12008-06-151-2/+4
* Allow NWINDOWS selection (CPU feature with model specific defaults)blueswir12008-06-071-2/+0
* MicroSparc I didn't have fsmuld opblueswir12008-05-291-0/+1
* Free tempsblueswir12008-05-271-109/+313
* More TCG type fixesblueswir12008-05-261-11/+8
* Fix cas on i386blueswir12008-05-261-1/+1
* remove absolete functionbellard2008-05-251-5/+0
* Nicer debug outputblueswir12008-05-251-0/+2
* More TCGv type fixes.pbrook2008-05-241-1/+2
* Fix ARM conditional branch bug.pbrook2008-05-241-31/+30
* Fix helper operand type mismatch.pbrook2008-05-241-1/+2
* Register op helpersblueswir12008-05-221-0/+5
* Generate better code for Sparc32 shiftsblueswir12008-05-171-6/+21
* Wrap long linesblueswir12008-05-121-86/+175
* Remove someexplicit alignment checks (initial patch by Fabrice Bellard)blueswir12008-05-111-44/+32
* Add a TODO fileblueswir12008-05-101-8/+0
* suppressed fixed registersbellard2008-05-101-21/+8
* Fix compiler warningsblueswir12008-05-101-3/+0
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