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* Sparc: avoid AREG0 wrappers for memory access helpersBlue Swirl2012-03-181-174/+0
| | | | | | | | | Adjust generation of load and store templates so that the functions take a parameter for CPUState instead of relying on global env. Remove wrappers. Move remaining memory helpers to ldst_helper.c. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: avoid AREG0 for memory access helpersBlue Swirl2012-03-181-1/+101
| | | | | | | Make memory access helpers take a parameter for CPUState instead of relying on global env. Introduce wrappers for load and store ops. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sparc: Don't overuse CPUStateAndreas Färber2012-03-141-2/+2
| | | | | | | | | Scripted conversion: sed -i "s/CPUState/CPUSPARCState/g" target-sparc/*.[hc] sed -i "s/#define CPUSPARCState/#define CPUState/" target-sparc/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
* Sparc: split load and store op helpersBlue Swirl2011-10-261-2416/+0
| | | | | | | Move load and store op helpers top ldst_helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: avoid AREG0 for division op helpersBlue Swirl2011-10-261-74/+0
| | | | | | | | Make [su]div{,cc} helpers take a parameter for CPUState instead of relying on global env. Move the functions to helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: avoid AREG0 for softint op helpers and Leon cache controlBlue Swirl2011-10-261-94/+0
| | | | | | | | | Make softint op helpers and Leon cache irq manager take a parameter for CPUState instead of relying on global env. Move the functions to int{32,64}_helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: split CWP and PSTATE op helpersBlue Swirl2011-10-231-488/+1
| | | | | | | Move CWP and PSTATE op helpers to win_helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: avoid AREG0 for lazy condition code helpersBlue Swirl2011-10-231-1/+1
| | | | | | | | Make lazy condition code helpers take a parameter for CPUState instead of relying on global env. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: split lazy condition code handling op helpersBlue Swirl2011-10-231-464/+0
| | | | | | | Move lazy condition code handling op helpers to cc_helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: split FPU and VIS op helpersBlue Swirl2011-10-231-743/+0
| | | | | | | | Move FPU op helpers to fop_helper.c. Move VIS op helpers to vis_helper.c, compile it only for Sparc64. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: fix coding styleBlue Swirl2011-10-231-452/+502
| | | | | | | Before the next patches, fix coding style of the areas affected. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: avoid AREG0 for raise_exception and helper_debugBlue Swirl2011-10-231-57/+43
| | | | | | | | | Make raise_exception() and helper_debug() take a parameter for CPUState instead of relying on global env. Move the functions to helper.c. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: move trivial functions from op_helper.cBlue Swirl2011-10-231-47/+0
| | | | | | | | | These functions don't need access to CPUState or already pass it, so relocating them from op_helper.c to helper.c and int64_helper.c is trivial. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: split helper.cBlue Swirl2011-10-231-1/+0
| | | | | | | | Move CPU init to cpu_init.c and interrupt handling to int32_helper.c for Sparc32 and int64_helper.c for Sparc64. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* softmmu_header: pass CPUState to tlb_fillBlue Swirl2011-10-011-4/+3
| | | | | | | Pass CPUState pointer to tlb_fill() instead of architecture local cpu_single_env hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc64: remove useless variableBlue Swirl2011-09-101-4/+2
| | | | | | | | | Remove a useless variable, spotted by clang analyzer: /src/qemu/target-sparc/op_helper.c:3904:18: warning: unused variable 'tmp' [-Wunused-variable] target_ulong tmp = val; The error message is actually incorrect since the variable is used. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl2011-08-071-1/+1
| | | | | | | | | Parameter is_softmmu (and its evil mutant twin brother is_softmuu) is not used in cpu_*_handle_mmu_fault() functions, remove them and adjust callers. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: fix non-faulting unassigned memory accessesBlue Swirl2011-08-011-17/+8
| | | | | | | | | | | | | | | | | Commit b14ef7c9ab41ea824c3ccadb070ad95567cca84e introduced cpu_unassigned_access() function. On Sparc, the function does not restore AREG0 used for global CPUState on function exit, causing bugs with non-faulting unassigned memory accesses. Alpha, Microblaze and MIPS are not affected. Fix by restoring AREG0 on exit. Remove excess saving by do_unassigned_access() functions. Also ignore unassigned accesses outside of CPU context. Reported-by: Bob Breuer <breuerr@mc.net> Tested-by: Bob Breuer <breuerr@mc.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* exec.h cleanupBlue Swirl2011-07-301-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move softmmu_exec.h include directives from target-*/exec.h to target-*/op_helper.c. Move also various other stuff only used in op_helper.c there. Define global env in dyngen-exec.h. For i386, move wrappers for segment and FPU helpers from user-exec.c to op_helper.c. Implement raise_exception_err_env() to handle dynamic CPUState. Move the function declarations to cpu.h since they can be used outside of op_helper.c context. LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and env_to_regs(). ARM: make raise_exception() static. Convert #include "exec.h" to #include "cpu.h" #include "dyngen-exec.h" and remove now unused target-*/exec.h. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: implement MMU miss traps on nonfaulting loadsTsuneo Saito2011-07-211-16/+20
| | | | | | | | | Nonfaulting loads should raise fast_data_access_MMU_miss traps as normal loads do. It is up to the guest OS kernel that detect MMU misses on nonfaulting load instructions and make them complete without signaling. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Fix unassigned memory access handlingBlue Swirl2011-07-201-6/+20
| | | | | | | | cea5f9a28faa528b6b1b117c9ab2d8828f473fef exposed bugs in unassigned memory access handling. Fix them by always passing CPUState to the handlers. Reported-by: Hervé Poussineau <hpoussin@reactos.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: treat UA2007 ASI_BLK_* as translating ASIs.Tsuneo Saito2011-07-201-1/+2
| | | | | | | | UA2007 ASI_BLK_* should be added in is_translating_asi(). Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: fix VIS1 SIMD signed compare instructionsTsuneo Saito2011-07-201-10/+13
| | | | | | | | | The destination registers of SIMD signed compare instructions (fcmp*<16|32>) are not FP registers but general purpose r registers. Comparisons should be freg_rs1 CMP freg_rs2, that were reversed. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: C99 comment fix for block-transfer ASIsTsuneo Saito2011-07-141-14/+14
| | | | | | | Fixed C99 comments on block-tranfer ASIs. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: Add JPS1 ASI_BLK_AIU[PS]L ASIs for ldfa and stfaTsuneo Saito2011-07-141-0/+4
| | | | | | | Support JPS1 little endian block transfer ASIs. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: Add UA2007 ASI_BLK_AIU[PS]L? ASIs for stfaTsuneo Saito2011-07-141-1/+5
| | | | | | | Support UA2007 block store ASIs for stfa instructions. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: Add UA2007 ASI_BLK_AIU[PS]L? ASIs for ldfaTsuneo Saito2011-07-141-1/+5
| | | | | | | Support UA2007 block load ASIs for ldfa instructions. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: Implement stfa/stdfa/stqfa instrcutions properlyTsuneo Saito2011-07-141-4/+11
| | | | | | | | This patch implements sparcv9 stfa/stdfa/stqfa instructions with non block-store ASIs. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC64: Implement ldfa/lddfa/ldqfa instructions properlyTsuneo Saito2011-07-141-5/+11
| | | | | | | | This patch implements sparcv9 ldfa/lddfa/ldqfa instructions with non block-load ASIs. Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc: move do_interrupt to helper.cBlue Swirl2011-06-261-240/+10
| | | | | | | | | | do_interrupt() was mixing CPUState pointer passed from caller and global env (AREG0). Fix by moving the function to helper.c. Introduce a helper for calling change_pstate() safely from outside of execution context. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc: fix coding style of the area to be movedBlue Swirl2011-06-261-14/+17
| | | | | | Before the next patch, fix coding style of the areas affected. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* cpu_loop_exit: avoid using AREG0Blue Swirl2011-06-261-3/+3
| | | | | | | Make cpu_loop_exit() take a parameter for CPUState instead of relying on global env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc32: dummy implementation of MXCC MMU breakpoint registersBlue Swirl2011-06-261-2/+24
| | | | | | | Add dummy registers for SuperSPARC MXCC MMU counter breakpoints, save and load all MXCC registers. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Delete unused tb_invalidate_page_rangeBlue Swirl2011-05-221-6/+0
| | | | | | | | | | | | tb_invalidate_page_range() was intended to be used to invalidate an area of a TB which the guest explicitly flushes from i-cache. However, QEMU detects writes to code areas where TBs have been generated, so his has never been useful. Delete the function, adjust callers. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Remove unused function parameter from cpu_restore_stateStefan Weil2011-04-201-1/+1
| | | | | | | | | The previous patch removed the need for parameter puc. Is is now unused, so remove it. Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
* SPARC: Fix Leon3 cache controlFabien Chouteau2011-02-011-4/+14
| | | | | | | | | | The "leon3_cache_control_int" (op_helper.c) function is called within leon3.c which leads to segfault error with the global "env". Now cache control is a CPU feature and everything is handled in op_helper.c. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* SPARC: Emulation of Leon3Fabien Chouteau2011-01-241-2/+154
| | | | | | | | | | | | Leon3 is an open-source VHDL System-On-Chip, well known in space industry (more information on http://www.gaisler.com). Leon3 is made of multiple components available in the GrLib VHDL library. Three devices are implemented: uart, timers and IRQ manager. You can find code for these peripherals in the grlib_* files. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc: fix NaN handlingBlue Swirl2011-01-181-22/+34
| | | | | | | | | | Fix several bugs in NaN handling: * e in fcmpe* only changes qNaN handling * FCC is unchanged if an exception is raised * clear previous FTT before setting it Reported-by: Mateusz Loskot <mateusz@loskot.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sparc: fix udiv(cc) and sdiv(cc)Aurelien Jarno2010-12-281-12/+42
| | | | | | | | | | | | | Since commit 5a4bb580cdb10b066f9fd67658b31cac4a4ea5e5, Xorg crashes on a Debian Etch image. The commit itself is fine, but it triggers a bug due to wrong computation of flags for udiv(cc) and sdiv(cc). This patch only compute cc_src2 for the cc version of udiv/sdiv. It also moves the update of cc_dst and cc_op to the helper, as it is faster doing it here when there is already an helper. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc: implement monitor command 'info tlb'Blue Swirl2010-12-191-10/+10
| | | | | | Use existing dump_mmu() to implement monitor command 'info tlb'. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64: fix udiv and sdiv insnsIgor V. Kovalenko2010-06-021-2/+2
| | | | | | | - truncate second operand to 32bit Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64: improve ldf and stf insnsIgor V. Kovalenko2010-06-021-0/+28
| | | | | | | - implemented block load/store primary/secondary with user privilege Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64: use symbolic name for MMU index v1Igor V. Kovalenko2010-06-021-12/+16
| | | | | | | | | | - use symbolic name for MMU index v0->v1: - change debug traces to DPRINTF_MMU - fix debug trace function names Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64: fix missing address masking v1Igor V. Kovalenko2010-06-021-2/+48
| | | | | | | | | | | | | - address masking for ldqf and stqf insns - address masking for lddf and stdf insns - address masking for translating ASI (Ultrasparc IIi) v0->v1: - move arch-specific code to helpers and drop more ifdefs at call sites using new helper asi_address_mask() - change user emulation to use asi_address_mask() Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc32 SuperSPARC MMU Breakpoint Action register (SS-20 OBP fix)Artyom Tarasenko2010-05-291-0/+1
| | | | | | | | | | SuperSPARC MMU Breakpoint Action register is used by OBP at boot The patch allows booting Solaris and some other OS with SPARCStation-20 OBP. Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64: fix user emulator buildBlue Swirl2010-05-291-0/+2
| | | | | | | | | | | | | Accesses with _nucleus prefix are not available when building user emulators: CC sparc64-linux-user/op_helper.o cc1: warnings being treated as errors /src/qemu/target-sparc/op_helper.c: In function 'helper_ldda_asi': /src/qemu/target-sparc/op_helper.c:3063: error: implicit declaration of function 'ldq_nucleus' Avoid making such accesses. Fixes breakage by 54a3c0f032abf93d1cedc75456af75401ac10360. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64: fix 128-bit atomic load from nucleus context v1Igor V. Kovalenko2010-05-291-5/+5
| | | | | | | - change 128-bit atomic loads to reference nucleus context v0->v1: dropped disassembler change Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64: flush translations on mmu context changeIgor V. Kovalenko2010-05-221-0/+6
| | | | | | | | | - two pairs of softmmu indexes bind softmmu tlb to cpu tlb in fault handlers using value of DMMU primary and secondary context registers, so we need to flush softmmu translations when context registers are changed Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64: fix pstate privilege bitsIgor V. Kovalenko2010-05-221-14/+10
| | | | | | | | | | | | - refactor code to handle hpstate only if available for current cpu - conditionally set hypervisor bit in hpstate register - reorder softmmu indices so user accessable ones go first, translation context macros supervisor() and hypervisor() adjusted as well - disable sparcv8 registers for TARGET_SPARC64 - fix cpu_mmu_index to use sparcv9 bits only Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sparc: Inline some generation of carry for ADDX/SUBX.Richard Henderson2010-05-201-1/+1
| | | | | | | | | | | Computing carry is trivial for some inputs. By avoiding an external function call, we generate near-optimal code for the common cases of add+addx (double-word arithmetic) and cmp+addx (a setcc pattern). Signed-off-by: Richard Henderson <rth@twiddle.net> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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