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* sparc: Clean up includesPeter Maydell2019-11-291-0/+1
| | | | | | | | | | Clean up includes so that osdep.h is included first and headers which it implies are not included manually. This commit was created with scripts/clean-includes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1453832250-766-7-git-send-email-peter.maydell@linaro.org
* target-sparc: Migrate CWP and PIL for SPARC64Peter Maydell2019-11-291-1/+4
| | | | | | | | | | | | | | | | | | | In SPARC32 the env->cwp and env->psrpil state is part of the PSR register, and gets migrated as part of that register. In SPARC64 this state is in separate CWP and PIL registers, but we were not doing anything to migrate those. Add the missing fields to the migration vmstate (which is a migration break, but without these fields migration is completely broken anyway). This change means that trying a save/load of a SPARC64 target at the boot rom prompt now produces a system which at least responds to keyboard input after the restore. Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* target-sparc: Use VMState arrays for SPARC64 TLB/MMU statePeter Maydell2019-11-291-295/+19
| | | | | | | | | | | Use VMState arrays for SPARC64 TLB/MMU state. This is a migration-break for SPARC64 (but not for SPARC32), which is acceptable because currently migration does not work for any SPARC64 machines due to the lack of any migration of interrupt controller state. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* target-sparc: Convert to VMStateDescriptionJuan Quintela2019-11-291-197/+444
| | | | | | | | | | | | | | | | | Convert the SPARC CPU from cpu_load/save functions to VMStateDescription. We preserve migration compatibility with the previous version (required for SPARC32 but not necessarily for SPARC64). Signed-off-by: Juan Quintela <quintela@redhat.com> [PMM: * Rebase and update to apply to master * VMSTATE_STRUCT_POINTER now takes type, not pointer-to-type * QEMUTimer* are migrated via VMSTATE_TIMER_PTR * Put CPUTimer vmstate struct inside TARGET_SPARC64 ifdef * Convert handling of PSR to use a vmstate_psr, like Alpha and ARM ] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* target-sparc: Don't flush TLB in cpu_load functionPeter Maydell2019-11-291-2/+0
| | | | | | | | There's no need to flush the TLB in the SPARC cpu_load function: we're guaranteed to be loading state into a fresh clean configuration. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
* cputlb: Change tlb_flush() argument to CPUStateAndreas Färber2014-03-131-1/+2
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* misc: move include files to include/qemu/Paolo Bonzini2012-12-191-1/+1
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-sparc: Don't overuse CPUStateAndreas Färber2012-03-141-2/+2
| | | | | | | | | Scripted conversion: sed -i "s/CPUState/CPUSPARCState/g" target-sparc/*.[hc] sed -i "s/#define CPUSPARCState/#define CPUState/" target-sparc/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
* target-sparc: Change fpr representation to doubles.Richard Henderson2011-10-261-14/+6
| | | | | | | | This allows a more efficient representation for 64-bit hosts. It should be about the same for 32-bit hosts, as we can still access the individual pieces of the double. Signed-off-by: Richard Henderson <rth@twiddle.net>
* Remove exec-all.h include directivesBlue Swirl2011-06-261-1/+1
| | | | | | Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc32: dummy implementation of MXCC MMU breakpoint registersBlue Swirl2011-06-261-0/+26
| | | | | | | Add dummy registers for SuperSPARC MXCC MMU counter breakpoints, save and load all MXCC registers. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc: Fix lazy flag calculation on interrupts, refactorBlue Swirl2010-05-091-2/+2
| | | | | | | | | | | | Recalculate Sparc64 CPU flags on interrupts, otherwise some earlier flags could be stored to pstate. Refactor PSR/CCR/CWP handling: concentrate the actual functions to op_helper.c. Thanks to Igor Kovalenko for reporting. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64: reimplement tick timers v4Igor V. Kovalenko2010-01-271-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | sparc64 timer has tick counter which can be set and read, and tick compare value used as deadline to fire timer interrupt. The timer is not used as periodic timer, instead deadline is set each time new timer interrupt is needed. v3 -> v4: - coding style v2 -> v3: - added missing timer debug output macro - CPUTimer struct and typedef moved to cpu.h - change CPU_SAVE_VERSION to 6, older save formats not supported v1 -> v2: - new conversion helpers cpu_to_timer_ticks and timer_to_cpu_ticks - save offset from clock source to implement cpu_tick_set_count - renamed struct sun4u_timer to CPUTimer - load and save cpu timers v0 -> v1: - coding style Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Sparc64: replace tsptr with helper routineIgor Kovalenko2009-08-041-1/+0
| | | | | | | | | | | | | | | | | | | tl and tsptr of members sparc64 cpu state must be changed simultaneously to keep trap state window in sync with current trap level. Currently translation of store to tl does not change tsptr, which leads to corrupt trap state on corresponding trap level. This patch removes tsptr from sparc64 cpu state and replaces all uses with call to helper routine. Changes v0->v1: - reimplemented helper routine with tcg generator - on cpu reset trap type and pstate are populated with power-on reset values, including tl=maxtl Signed-off-by: igor.v.kovalenko@gmail.com Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64 name mmu registers and general cleanupIgor Kovalenko2009-07-271-8/+8
| | | | | | | | | | | | | | | | | | | - add names to mmu registers, this helps understanding the code which uses/modifies them. - fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries - extract demap_tlb routine (code duplication) - extract replace_tlb routine (code duplication) - flush qemu tlb translations when replacing sparc64 mmu tlb entries I have no test case which demands flushing qemu translations, and this patch should have no other visible changes to runtime. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
* Convert machine registration to use module init functionsAnthony Liguori2009-05-211-22/+0
| | | | | | This cleans up quite a lot of #ifdefs, extern variables, and other ugliness. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Remove unnecessary trailing newlinesblueswir12008-12-131-2/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
* Add a generic Niagara machineblueswir12008-09-261-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5329 c046a42c-6fe2-441c-8c8c-71466251a162
* Handle wrapped registers correctly when savingblueswir12008-08-011-1/+11
| | | | | | | | | Fix typo Save and load interrupt_index and pil_in Original patch by Luis Pureza git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4980 c046a42c-6fe2-441c-8c8c-71466251a162
* Make MAXTL dynamic, bounds check tl when indexingblueswir12008-07-251-5/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4942 c046a42c-6fe2-441c-8c8c-71466251a162
* Sparc32: save/load all MMU registers, Sparc64: add CPU save/loadblueswir12008-07-241-3/+109
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4938 c046a42c-6fe2-441c-8c8c-71466251a162
* Add T1 and T2 CPUs, add a Sun4v machineblueswir12008-07-221-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4923 c046a42c-6fe2-441c-8c8c-71466251a162
* Allow NWINDOWS selection (CPU feature with model specific defaults)blueswir12008-06-071-2/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4690 c046a42c-6fe2-441c-8c8c-71466251a162
* remove target ifdefs from vl.caurel322008-05-041-0/+102
(Glauber Costa) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4327 c046a42c-6fe2-441c-8c8c-71466251a162
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