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* Sparc64: replace tsptr with helper routineIgor Kovalenko2009-08-041-1/+0
| | | | | | | | | | | | | | | | | | | tl and tsptr of members sparc64 cpu state must be changed simultaneously to keep trap state window in sync with current trap level. Currently translation of store to tl does not change tsptr, which leads to corrupt trap state on corresponding trap level. This patch removes tsptr from sparc64 cpu state and replaces all uses with call to helper routine. Changes v0->v1: - reimplemented helper routine with tcg generator - on cpu reset trap type and pstate are populated with power-on reset values, including tl=maxtl Signed-off-by: igor.v.kovalenko@gmail.com Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64 name mmu registers and general cleanupIgor Kovalenko2009-07-271-8/+8
| | | | | | | | | | | | | | | | | | | - add names to mmu registers, this helps understanding the code which uses/modifies them. - fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries - extract demap_tlb routine (code duplication) - extract replace_tlb routine (code duplication) - flush qemu tlb translations when replacing sparc64 mmu tlb entries I have no test case which demands flushing qemu translations, and this patch should have no other visible changes to runtime. Signed-off-by: igor.v.kovalenko@gmail.com -- Kind regards, Igor V. Kovalenko
* Convert machine registration to use module init functionsAnthony Liguori2009-05-211-22/+0
| | | | | | This cleans up quite a lot of #ifdefs, extern variables, and other ugliness. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Remove unnecessary trailing newlinesblueswir12008-12-131-2/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
* Add a generic Niagara machineblueswir12008-09-261-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5329 c046a42c-6fe2-441c-8c8c-71466251a162
* Handle wrapped registers correctly when savingblueswir12008-08-011-1/+11
| | | | | | | | | Fix typo Save and load interrupt_index and pil_in Original patch by Luis Pureza git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4980 c046a42c-6fe2-441c-8c8c-71466251a162
* Make MAXTL dynamic, bounds check tl when indexingblueswir12008-07-251-5/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4942 c046a42c-6fe2-441c-8c8c-71466251a162
* Sparc32: save/load all MMU registers, Sparc64: add CPU save/loadblueswir12008-07-241-3/+109
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4938 c046a42c-6fe2-441c-8c8c-71466251a162
* Add T1 and T2 CPUs, add a Sun4v machineblueswir12008-07-221-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4923 c046a42c-6fe2-441c-8c8c-71466251a162
* Allow NWINDOWS selection (CPU feature with model specific defaults)blueswir12008-06-071-2/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4690 c046a42c-6fe2-441c-8c8c-71466251a162
* remove target ifdefs from vl.caurel322008-05-041-0/+102
(Glauber Costa) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4327 c046a42c-6fe2-441c-8c8c-71466251a162
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