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* SPARC: Emulation of Leon3Fabien Chouteau2011-01-241-0/+1
| | | | | | | | | | | | Leon3 is an open-source VHDL System-On-Chip, well known in space industry (more information on http://www.gaisler.com). Leon3 is made of multiple components available in the GrLib VHDL library. Three devices are implemented: uart, timers and IRQ manager. You can find code for these peripherals in the grlib_* files. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sparc: fix udiv(cc) and sdiv(cc)Aurelien Jarno2010-12-281-0/+2
| | | | | | | | | | | | | Since commit 5a4bb580cdb10b066f9fd67658b31cac4a4ea5e5, Xorg crashes on a Debian Etch image. The commit itself is fine, but it triggers a bug due to wrong computation of flags for udiv(cc) and sdiv(cc). This patch only compute cc_src2 for the cc version of udiv/sdiv. It also moves the update of cc_dst and cc_op to the helper, as it is faster doing it here when there is already an helper. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sparc: Inline some generation of carry for ADDX/SUBX.Richard Henderson2010-05-201-1/+1
| | | | | | | | | | | Computing carry is trivial for some inputs. By avoiding an external function call, we generate near-optimal code for the common cases of add+addx (double-word arithmetic) and cmp+addx (a setcc pattern). Signed-off-by: Richard Henderson <rth@twiddle.net> Acked-by: Artyom Tarasenko <atar4qemu@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sparc: Fix compilation with --enable-debug.Richard Henderson2010-05-191-1/+1
| | | | | | | Return a target_ulong from compute_C_icc to match the width of the users. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* sparc64: use helper_wrpil to check pending irq on writeIgor V. Kovalenko2010-01-081-0/+1
| | | | | Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Use dynamical computation for condition codesBlue Swirl2009-05-101-0/+2
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* TCG variable type checking.pbrook2008-11-171-109/+101
| | | | | | | Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
* Implement UA2005 hypervisor trapsblueswir12008-09-261-2/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5327 c046a42c-6fe2-441c-8c8c-71466251a162
* Add software and timer interrupt supportblueswir12008-09-221-0/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5299 c046a42c-6fe2-441c-8c8c-71466251a162
* Use the new concat_i32_i64 op for std and stdablueswir12008-09-211-1/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5281 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert rest of ops using float32 to TCG, remove FT0 and FT1blueswir12008-09-101-11/+8
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5193 c046a42c-6fe2-441c-8c8c-71466251a162
* Partially convert float128 conversion ops to TCGblueswir12008-09-101-4/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5192 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert basic 64 bit VIS ops to TCGblueswir12008-09-101-9/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5191 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert basic 32 bit VIS ops to TCGblueswir12008-09-101-15/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5190 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert basic float32 ops to TCGblueswir12008-09-101-18/+29
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5189 c046a42c-6fe2-441c-8c8c-71466251a162
* Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCGblueswir12008-09-091-2/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix Sparc64 boot on i386 host:blueswir12008-08-291-9/+0
| | | | | | | | | | | - move do_interrupt() back to op_helper.c - move non-helper prototypes from helper.h to exec.h - move some prototypes from cpu.h to exec.h - do not export either set_cwp() or cpu_set_cwp() from op_helper.c, but instead provide inline functions git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5109 c046a42c-6fe2-441c-8c8c-71466251a162
* Implement nucleus quad lddablueswir12008-07-191-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4902 c046a42c-6fe2-441c-8c8c-71466251a162
* Move non-op functions from op_helper.c to helper.c and vice versa.blueswir12008-05-271-0/+1
| | | | | | | Rearrange interrupt handling to match other targets. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4590 c046a42c-6fe2-441c-8c8c-71466251a162
* Register op helpersblueswir12008-05-221-93/+96
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4534 c046a42c-6fe2-441c-8c8c-71466251a162
* Move prototype back to avoid a compiler warningblueswir12008-05-121-1/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4443 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix compiler warningsblueswir12008-05-101-0/+9
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4404 c046a42c-6fe2-441c-8c8c-71466251a162
* CPU feature selection supportblueswir12008-05-091-20/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4399 c046a42c-6fe2-441c-8c8c-71466251a162
* Complete the TCG conversionblueswir12008-05-041-0/+7
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4323 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert align checks to TCGblueswir12008-03-211-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4097 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert save, restore, saved, restored, and flushw to TCGblueswir12008-03-211-0/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4092 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert other float and VIS ops to TCGblueswir12008-03-211-0/+96
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4091 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert udiv and sdiv ops to TCGblueswir12008-03-181-0/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4088 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert CCR and CWP ops to TCGblueswir12008-03-181-0/+4
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4086 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert array8/16/32 and alignaddr to TCGblueswir12008-03-181-0/+4
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4085 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert ldfsr and stfsr to TCGblueswir12008-03-151-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4067 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert exception ops to TCGblueswir12008-03-061-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4022 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert float helpers to TCG, fix fabsq in the processblueswir12008-03-041-0/+39
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4014 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert tick operations to TCGblueswir12008-03-021-0/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4011 c046a42c-6fe2-441c-8c8c-71466251a162
* Modify Sparc32/64 to use TCGblueswir12008-02-241-0/+32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3989 c046a42c-6fe2-441c-8c8c-71466251a162
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