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* Fix typo.pbrook2008-05-301-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
* Move clone() register setup to target specific code. Handle fork-like clone.pbrook2008-05-301-0/+12
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
* MicroSparc I didn't have fsmuld opblueswir12008-05-291-2/+3
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* Push common interrupt variables to cpu-defs.h (Glauber Costa)bellard2008-05-291-2/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
* moved halted field to CPU_COMMONbellard2008-05-281-1/+0
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* Wrap long linesblueswir12008-05-121-1/+1
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* Remove duplicated fieldblueswir12008-05-101-1/+0
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* suppressed fixed registersbellard2008-05-101-2/+5
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* Fix compiler warningsblueswir12008-05-101-7/+7
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* CPU feature selection supportblueswir12008-05-091-3/+27
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* Complete the TCG conversionblueswir12008-05-041-4/+2
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* Document the shift valuesblueswir12008-04-231-6/+12
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* Move CPU stuff unrelated to translation to helper.cblueswir12008-03-291-0/+1
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* Convert mulscc to TCG, add cc_src2blueswir12008-03-161-1/+1
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* Convert condition code changing versions of add, sub, logic, and div to TCGblueswir12008-03-131-0/+5
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* Convert exception ops to TCGblueswir12008-03-061-1/+0
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* Convert Sparc64 trap state ops to TCGblueswir12008-03-051-4/+8
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* Convert tick operations to TCGblueswir12008-03-021-3/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4011 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix remote debugger memory access problems reported by Matthias Steinblueswir12008-02-141-5/+8
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* Sparc32 MMU register fixes (Robert Reif)blueswir12008-02-111-0/+4
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3979 c046a42c-6fe2-441c-8c8c-71466251a162
* Use slavio base as boot prom address, rearrange sun4m init codeblueswir12007-11-281-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3747 c046a42c-6fe2-441c-8c8c-71466251a162
* 128-bit float support for user modeblueswir12007-11-251-0/+3
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* More MMU registers (Robert Reif)blueswir12007-11-251-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3738 c046a42c-6fe2-441c-8c8c-71466251a162
* added cpu_model parameter to cpu_init()bellard2007-11-101-6/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
* CPU specific boot mode (Robert Reif)blueswir12007-11-071-1/+1
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* Sparc64 hypervisor modeblueswir12007-10-141-4/+35
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* SuperSparc MXCC support (Robert Reif)blueswir12007-10-141-1/+4
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3397 c046a42c-6fe2-441c-8c8c-71466251a162
* Replace is_user variable with mmu_idx in softmmu core,j_mayer2007-10-141-0/+11
| | | | | | | | | | | | | | allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
* Unify '-cpu ?' option.j_mayer2007-10-121-0/+1
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* Move get_sp_from_cpustate from cpu.h to target_signal.h.ths2007-09-271-12/+0
| | | | | | | Enable sigaltstack processing for more architectures. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3253 c046a42c-6fe2-441c-8c8c-71466251a162
* linux-user sigaltstack() syscall, by Thayne Harbaugh.ths2007-09-271-0/+12
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* CPU boot modeblueswir12007-09-241-0/+1
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* Detabifyblueswir12007-09-201-26/+26
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3195 c046a42c-6fe2-441c-8c8c-71466251a162
* find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths2007-09-161-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix Sparc32 interrupt handlingblueswir12007-08-041-1/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3110 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix retry and done ops, trap handlingblueswir12007-07-081-4/+2
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* Report normalised CWP values to userland and GDB, not internal representationblueswir12007-07-071-2/+8
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3052 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix wrong number of clean/saveable windows, match Linux startup register valuesblueswir12007-07-071-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3050 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix Sparc64 page sizeblueswir12007-07-071-1/+1
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* Move target-specific defines to the target directories.ths2007-06-031-0/+6
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* Enable 36-bit physical address space also on 32-bit hostsblueswir12007-06-011-0/+2
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* Separate fault for code access to unassigned memoryblueswir12007-05-271-0/+2
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* Implement Sparc64 CPU timers using ptimersblueswir12007-05-251-0/+5
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* Use full 36-bit physical address space on SS10blueswir12007-05-191-1/+1
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* Enable faults for unassigned memory accesses and unimplemented ASIsblueswir12007-05-171-0/+2
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* Report unassigned memory access to CPU (not enabled yet)blueswir12007-05-061-1/+4
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* Sparc64 update: more VIS opsblueswir12007-04-221-0/+3
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* Alignment check mechanism (not fully enabled yet) (Aurelien Jarno)blueswir12007-04-131-0/+2
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* Fix stdfq op (Aurelien Jarno)blueswir12007-04-051-1/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2604 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix Sparc lda/ldda/sta/stda asi handling, fault on misaligned register ↵blueswir12007-04-011-1/+1
| | | | | | ldd/std and illegal cwp on wrpsr (Aurelien Jarno) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2568 c046a42c-6fe2-441c-8c8c-71466251a162
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