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* target-sh4: make the initial value of SR easier to readaurel322008-12-132-1/+5
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6016 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: don't disable FPU instructions in user modeaurel322008-12-131-1/+1
| | | | | | | | Based on a patch from Lionel Landwerlin. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6015 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: disable debug codeaurel322008-12-131-1/+3
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6014 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: add prefi, icbi, syncoaurel322008-12-132-0/+27
| | | | | | (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6013 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: add SH7785 as CPU optionaurel322008-12-132-1/+8
| | | | | | (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6012 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: remove 2 warningsaurel322008-12-112-4/+4
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5993 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: Add SH bit handling to TLBaurel322008-12-101-6/+6
| | | | | | | | | | | | | | | | This patch adds SH bit handling to sh4's TLB, which is a part of MMU functionality that had not been implemented in qemu. Additionally, increment_urc() call in cpu_load_tlb() is deleted, because the specification explicitly says that URC is not incremented by an LDTLB instruction (at Section 3 of SH7751 Hardware manual(REJ09B0370-0400)). Even though URC is not needed to be strictly same as HW because it is a random number, this condition is not negligible. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5971 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: check FD bit for FP instructionsaurel322008-12-101-6/+23
| | | | | | | | Based on a patch from Vladimir Prus <vladimir@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5970 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: kill a few warningsaurel322008-12-071-2/+2
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5938 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: Implement FD bitaurel322008-12-074-5/+42
| | | | | | | | | | | | | | | | | | SH4 manual say that if a floating point instruction is executed while FD bit in the status register is 1, an exception should be raised. QEMU presently does not do that, so the kernel does not initialize FP state for any thread, nor does it save/restore FP state. The most apparent consequence is that while recent gcc/libc expect double-precision mode to be set by kernel, they run in single-precision mode, and all FP code produces wrong values. This patch fixes this. It also fixes a couple of places where PC was not updated before handling an exception, although both those places deal with invalid instruction and don't lead to any user-visible bugs. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5937 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).balrog2008-12-071-12/+0
| | | | | | | | | | | | | | | | | | | | | Main purpose of this is to delete *physical = address & 0x1fffffff; at target-sh4/helper.c:449, using new mmio rule introduced by #5849 This masking is a nice trick to realize P4/A7 duality of SH registers. But, IMHO, it is logically wrong. Most of SH4 cpu control registers in P4 area(0xfc000000...0xffffffff) have one more address called A7 which is usually P4 address with upper 3bits masked. This is an address only appears in TLB's physical address part. Current code use trick writing drivers as if they are really in A7 (that's why you see many *_A7 in hw/sh*.c), and using translation P4 to A7. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5935 c046a42c-6fe2-441c-8c8c-71466251a162
* SH: On-chip PCI controller support (Takashi YOSHII).balrog2008-12-071-0/+3
| | | | | | | | | | This patch adds SuperH on-chip PCI controller(PCIC) support. Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5927 c046a42c-6fe2-441c-8c8c-71466251a162
* Remove FORCE_RET() and RETURN()aurel322008-12-071-2/+0
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5923 c046a42c-6fe2-441c-8c8c-71466251a162
* Common cpu_loop_exit prototypeaurel322008-11-301-2/+0
| | | | | | | | | | | All archs use the same cpu_loop_exit, so move the prototype in a common header. i386 was carrying a __hidden attribute, but that was empty for this arch anyway. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5820 c046a42c-6fe2-441c-8c8c-71466251a162
* Use sys-queue.h for break/watchpoint managment (Jan Kiszka)aliguori2008-11-251-2/+2
| | | | | | | | | | | | | This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying the code and also fixing a use after release issue in cpu_break/watchpoint_remove_all. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5799 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: fix 64-bit fmov to/from memoryaurel322008-11-221-29/+33
| | | | | | | | | | | When loading/storing a register pair, the even-numbered register always maps to the low 32 bits of memory independently of target endian configuration. Signed-off-by: Mans Rullgard <mans@mansr.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5773 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: fix TLB/MMU emulationaurel322008-11-211-36/+29
| | | | | | | | Based on a patch from Vladimir Prus and comments from Shin-ichiro KAWASAKI. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5770 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: fix fldi0/fldi1aurel322008-11-201-4/+2
| | | | | | | | | fldi0/fldi1 should be executed as a nop if FPSCR.FR is set instead of generating an exception. Reported by Laurent Desnogues. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5759 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: map FP registers as TCG variablesaurel322008-11-191-106/+43
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5758 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: use CPU_Float/CPU_Double instead of ugly castsaurel322008-11-191-40/+102
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5757 c046a42c-6fe2-441c-8c8c-71466251a162
* Refactor and enhance break/watchpoint API (Jan Kiszka)aliguori2008-11-181-3/+4
| | | | | | | | | | | | | | | | | | | | | This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow the succeeding enhancements this series comes with. First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switching to dynamically allocated data structures that are kept in linked lists. This also allows to return a stable reference to the related objects, required for later introduced x86 debug register support. Breakpoints and watchpoints are stored with their full information set and an additional flag field that makes them easily extensible for use beyond pure guest debugging. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5738 c046a42c-6fe2-441c-8c8c-71466251a162
* Refactor translation block CPU state handling (Jan Kiszka)aliguori2008-11-181-0/+11
| | | | | | | | | | | | | | | This patch refactors the way the CPU state is handled that is associated with a TB. The basic motivation is to move more arch specific code out of generic files. Specifically the long #ifdef clutter in tb_find_fast() has to be overcome in order to avoid duplicating it for the gdb watchpoint fixes (patch "Restore pc on watchpoint hits"). Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5736 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)aliguori2008-11-181-5/+7
| | | | | | | | | | | as macros should be avoided when possible. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
* TCG variable type checking.pbrook2008-11-173-308/+313
| | | | | | | Signed-off-by: Paul Brook <paul@codesourcery.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix undeclared symbol warnings from sparseblueswir12008-10-261-2/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5539 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: Implement MOVUA.Laurel322008-10-121-0/+11
| | | | | | | | | * target-sh4/translate.c (_decode_opc): Implement MOVUA.L. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5473 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: fix single-steppingaurel322008-10-121-0/+1
| | | | | | | | | * target-sh/translate.c (gen_intermediate_code_internal): If singlestep is enabled, update PC before stopping. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5472 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: Fix swap.baurel322008-10-121-1/+4
| | | | | | | | | | | | | | | The SH4 manual documents the swap.b instruction as follows: SWAP.B Rm,Rn Rm → swap lower 2 bytes → Rn Current QEMU code, in addition to the above, also clears the high 16 bits. The immediate breakage I saw is that htonl function applied to netmask of 255.255.255.0 gives 0, which breaks all networking. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5471 c046a42c-6fe2-441c-8c8c-71466251a162
* Silence some warnings about no value returned from non-void functionblueswir12008-10-051-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5430 c046a42c-6fe2-441c-8c8c-71466251a162
* Add concat_i32_i64 op.pbrook2008-09-211-6/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
* Suppress gcc 4.x -Wpointer-sign (included in -Wall) warningsblueswir12008-09-201-2/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5275 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: Privilege check for instructionsaurel322008-09-151-24/+43
| | | | | | | | | This patch adds check for all SH4 instructions which are executed only in privileged mode. (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5224 c046a42c-6fe2-441c-8c8c-71466251a162
* qemu sh4 nptl supportaurel322008-09-151-0/+5
| | | | | | (Michael Trimarchi) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5223 c046a42c-6fe2-441c-8c8c-71466251a162
* sh4: doesn't set the cpu_model_straurel322008-09-151-0/+1
| | | | | | | | Fix setting of cpu_model_str for sh4 (Michael Trimarchi) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5222 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: sleep instruction bug fixaurel322008-09-153-3/+4
| | | | | | | | | fix a bug on 'sleep' instruction, which have caused halt of idle task. As i386 'hlt' instruction does, it should save PC before sleep. (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5220 c046a42c-6fe2-441c-8c8c-71466251a162
* sh4: CPU versioning.aurel322008-09-022-0/+76
| | | | | | | | | | | | | | | | | | | Trivial patch adding CPU listing and the ability to do per-subtype CVR/PVR/PRR values. Presently SH7750R and SH7751R definitions are provided, as these are the ones in present use in-tree. The CVR value for SH7751R is intentionally restricted so the kernel boots, though this will want to be switched to the proper CVR value once system emulation has sufficiently stabilized. This also makes it trivial to abstract subtype specific registers like MMU_PTEA and to set up feature bits in line with the kernel probing for things like conditionalizing FPU/DSP context. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5133 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: fix a regression introduced in r5122aurel322008-09-021-1/+1
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5132 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: Remove dyngen leftoversaurel322008-09-013-16/+1
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5126 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: final conversion to TCGaurel322008-09-014-28/+14
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5125 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: convert floating-point ops to TCGaurel322008-09-015-420/+421
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5124 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: Remove most uses of cpu_T[0] and cpu_T[1]aurel322008-09-011-181/+427
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5122 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: TCG optimisationsaurel322008-09-011-349/+236
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5121 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: Convert remaining non-fp ops to TCGaurel322008-09-015-153/+130
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5120 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: Convert shift functions to TCGaurel322008-08-302-24/+9
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5119 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: convert control/status register load/store to TCGaurel322008-08-304-82/+69
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5118 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: Convert memory loads/stores to TCGaurel322008-08-302-126/+58
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5117 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: convert some more arithmetics ops to TCGaurel322008-08-305-193/+86
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5116 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: convert a few helpers to TCGaurel322008-08-294-58/+52
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5112 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: convert branch/jump instructions to TCGaurel322008-08-292-118/+54
| | | | | | (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5111 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: convert simple compare instructions to TCGaurel322008-08-292-87/+53
| | | | | | (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5108 c046a42c-6fe2-441c-8c8c-71466251a162
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