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* Remove exec-all.h include directivesBlue Swirl2011-06-263-3/+0
| | | | | | Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Move cpu_has_work and cpu_pc_from_tb to cpu.hBlue Swirl2011-06-262-11/+13
| | | | | | | Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is needed by later patches. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* exec.h: fix coding style and change cpu_has_work to return boolBlue Swirl2011-06-261-2/+2
| | | | | | | | | Before the next patch, fix coding style of the areas affected. Change the type of the return value from cpu_has_work() and qemu_cpu_has_work() to bool. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* cpu_loop_exit: avoid using AREG0Blue Swirl2011-06-261-5/+5
| | | | | | | Make cpu_loop_exit() take a parameter for CPUState instead of relying on global env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Remove unused function parameter from cpu_restore_stateStefan Weil2011-04-201-1/+1
| | | | | | | | | The previous patch removed the need for parameter puc. Is is now unused, so remove it. Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
* Remove unused function parameters from gen_pc_load and rename the functionStefan Weil2011-04-201-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Function gen_pc_load was introduced in commit d2856f1ad4c259e5766847c49acbb4e390731bd4. The only reason for parameter searched_pc was a debug statement in target-i386/translate.c. Parameter puc was needed by target-sparc until commit d7da2a10402f1644128b66414ca8f86bdea9ae7c. Remove searched_pc from the debug statement and remove both parameters from the parameter list of gen_pc_load. As the function name gen_pc_load was also misleading, it is now called restore_state_to_opc. This new name was suggested by Peter Maydell, thanks. v2: Remove last parameter, too, and rename the function. v3: Fix [] typo in target-arm/translate.c. Fix wrong SHA1 object name in commit message (copy+paste error). Cc: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Stefan Weil <weil@mail.berlios.de>
* target-sh4: get rid of CPU_{Float,Double}UAurelien Jarno2011-04-122-158/+92
| | | | | | | | SH4 is always using softfloat, so it's possible to have helpers directly taking float32 or float64 value. This allow to get rid of conversions through CPU_{Float,Double}U. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Fix conversions from pointer to tcg_target_longStefan Weil2011-04-101-1/+1
| | | | | | | | | | | | tcg_gen_exit_tb takes a parameter of type tcg_target_long, so the type casts of pointer to long should be replaced by type casts of pointer to tcg_target_long (suggested by Blue Swirl). These changes are needed for build environments where sizeof(long) != sizeof(void *), especially for w64. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* inline cpu_halted into sole callerPaolo Bonzini2011-03-131-10/+0
| | | | | | | | All implementations are now the same, and there is only one caller, so inline the function there. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sh4: move intr_at_halt out of cpu_halted()Aurelien Jarno2011-03-034-4/+4
| | | | | | | | | | | | | | All targets except SH4 have the same cpu_halted() routine, and it has only one caller. It is therefore a good candidate for inlining. The difference is the handling of the intr_at_halt, which is necessary to ignore SR.BL when sleeping. Move intr_at_halt handling out of it, by setting this variable while executing the sleep instruction, and clearing it when the CPU has been woken-up by an interrupt, whatever the state of SR.BL. Also rename this variable in_sleep. Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: fix negcAurelien Jarno2011-02-041-2/+2
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: update PTEH upon MMU exceptionAlexandre Courbot2011-01-261-0/+4
| | | | | | | | Update the PTEH register to contain the VPN at which an MMU exception occured as specified by the SH4 reference. Signed-off-by: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* sh4: implement missing mmaped TLB read functionsAurelien Jarno2011-01-262-0/+82
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* sh4: implement missing mmaped TLB write functionsAurelien Jarno2011-01-262-3/+67
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: fix index of address read error exceptionAlexandre Courbot2011-01-251-1/+1
| | | | | | | Exception index of address read error should be 0x0e0. Signed-off-by: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: fix TLB invalidation codeAlexandre Courbot2011-01-251-2/+2
| | | | | | | | In cpu_sh4_invalidate_tlb, the UTLB was invalidated twice and the ITLB left unchaged, probably because of some unfortunate copy/paste. Signed-off-by: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: implement negc using TCGAurelien Jarno2011-01-163-17/+15
| | | | | | | Using setcond it's now possible to generate a relatively short negc instruction in TCG. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: use rotl/rotr when possibleAurelien Jarno2011-01-161-5/+3
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: correct use of ! and &Aurelien Jarno2011-01-151-2/+2
| | | | | | | | Fix wrong usage of ! and & in MMU related functions. Thanks to Blue Swirl for reporting the issue. Reported-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: use setcond when possibleAurelien Jarno2011-01-141-29/+27
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: log instructions start in TCG codeAurelien Jarno2011-01-141-0/+4
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: simplify comparisons after a 'and' opAurelien Jarno2011-01-141-3/+3
| | | | | | | | When a TCG variable is anded with a value and the compared with the same value, we can simply invert the comparison and compare it with 0. The generated code is smaller. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: fix reset on r2dAurelien Jarno2011-01-142-18/+16
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: optimize exceptionsAurelien Jarno2011-01-142-15/+12
| | | | | | | As exception is not the normal path, don't bother saving PC, before raising one, instead rely on code retranslation to get the CPU state. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: add ftrv instructionAurelien Jarno2011-01-143-0/+38
| | | | | | | Add the ftrv XMTRX,FVn instruction, which computes the 4-row x 4-column matrix XMTRX by the 4-dimensional vector FVn. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: add fipr instructionAurelien Jarno2011-01-143-0/+33
| | | | | | | Add the fipr FVm,FVn instruction, which computes the inner products of a 4-dimensional single precision floating-point vector. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: implement FPU exceptionsAurelien Jarno2011-01-141-22/+136
| | | | | | | | | | | FPU exception support where not implemented on SH4. Implement them by clearing the softfloat exceptions flags before an FP instruction (the SH4 FPU also clear them before an instruction), and calling a function to update the FPSCR register after an FP instruction. This function update the corresponding FPSCR bits (both flags and cumulative flags) and trigger exception if enabled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: implement flush-to-zeroAurelien Jarno2011-01-142-0/+2
| | | | | | | When the FPSCR.DN bit is set, the SH4 FPU treat denormalized numbers as zero. Enable the corresponding softfloat option when this bit is set. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: define FPSCR constantsAurelien Jarno2011-01-143-9/+37
| | | | | | | Define FPSCR constants for all field and use them instead of hardcoded values. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: use default-NaN modeAurelien Jarno2011-01-141-0/+1
| | | | | | | SH4 FPU doesn't propagate NaN, and instead always regenerate new ones. Enable the default-NaN mode by default. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: fix fpu disabled/illegal exceptionAurelien Jarno2011-01-111-10/+18
| | | | | | | | | | | Illegal instructions in a slot delay should generate a slot illegal instruction exception instead of an illegal instruction exception. The current PC should be saved before generating such an exception, but should not be corrected if in a delay slot, given it's already done in the exception handler do_interrupt(). Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: improve TLBAurelien Jarno2011-01-101-21/+44
| | | | | | | | | | | | | | | | | SH4 is using 16-bit instructions which means most of the constants are loaded through a constant pool at the end of the subroutine. The same memory page is therefore accessed in exec and read mode. With the current implementation, a QEMU TLB entry is set to read or read/write mode after an UTLB search and to exec mode after an ITLB search, which causes a lot of TLB exceptions to switch from read or read/write to exec and vice versa. This patch optimizes that by already setting the QEMU TLB entry in read or read/write mode when an UTLB entry is copied into ITLB (during an ITLB miss). This improve the emulation speed by about 14%. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: implement writes to mmaped ITLBAurelien Jarno2011-01-092-0/+21
| | | | | | | | | | | Some Linux kernels seems to implement ITLB/UTLB flushing through by writing all TLB entries through the memory mapped interface instead of writing one to MMUCR.TI. Implement memory mapped ITLB write interface so that such kernels can boot. This fixes https://bugs.launchpad.net/bugs/700774 . Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-xxx: Use fprintf_function (format checking)Stefan Weil2010-10-302-2/+3
| | | | | | | | | | | | | fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sh4: Add support for ldc & stc with sgrAlexandre Courbot2010-07-121-0/+2
| | | | | | | | | | | | | | | Add support for the following missing priviledged intructions: For SH4: - stc sgr, Rn - stc.l sgr, @-Rn For SH4A: - ldc Rm, sgr - ldc.l @Rm+, sgr Signed-off-by: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: Split the LDST macro into 2 sub-macrosAlexandre Courbot2010-07-121-2/+6
| | | | | | | | | | | The LDST macro is used to generate ldc and stc instructions that work with a specific register. However, the SGR register only supports stc up to SH4A, which supports both stc and ldc. This patch creates two sub-macros named LD and ST that handle generating ldc and stc instructions separately, and redeclares LDST to use these sub-macro. Signed-off-by: Alexandre Courbot <gnurou@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* remove exec-all.h inclusion from cpu.hPaolo Bonzini2010-07-031-1/+0
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* move cpu_pc_from_tb to target-*/exec.hPaolo Bonzini2010-07-032-6/+6
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sh4: Remove duplicate CPU log.Richard Henderson2010-05-051-6/+0
| | | | | | | Logging for -d cpu is done in generic code. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* remove TARGET_* defines from translate-all.cPaolo Bonzini2010-04-081-0/+2
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Replace assert(0) with abort() or cpu_abort()Blue Swirl2010-03-183-5/+5
| | | | | | | | | When building with -DNDEBUG, assert(0) will not stop execution so it must not be used for abnormal termination. Use cpu_abort() when in CPU context, abort() otherwise. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Large page TLB flushPaul Brook2010-03-171-1/+2
| | | | | | | | | | | | | | | | | | QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>
* Target specific usermode cleanupPaul Brook2010-03-121-0/+2
| | | | | | Disable various target specific code that is only relevant to system emulation. Signed-off-by: Paul Brook <paul@codesourcery.com>
* Remove cpu_get_phys_page_debug from userspace emulationPaul Brook2010-03-121-5/+0
| | | | | | cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it. Signed-off-by: Paul Brook <paul@codesourcery.com>
* Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.Richard Henderson2010-03-121-0/+3
| | | | | | | | | | Removes a set of ifdefs from exec.c. Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other than Alpha. This will be used for page_find_alloc, which is supposed to be using virtual addresses in the first place. Signed-off-by: Richard Henderson <rth@twiddle.net>
* Fix incorrect exception_index useBlue Swirl2010-02-141-1/+1
| | | | | | | | | | env->exception_index should be cleared with -1, not 0. See also 821b19fe923ac49a24cdb4af902584fdd019cee6. Spotted by Igor Kovalenko. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-sh4: MMU: separate execute and read/write permissionsAurelien Jarno2010-02-091-21/+6
| | | | | | | | | On SH4, the ITLB and UTLB configurations are memory mapped, so loading ITLB entries from UTLB has to be simulated correctly. For that the QEMU TLB has to be handle the execute (ITLB) and read/write permissions (UTLB) seperately. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: MMU: fix store queue addressesAurelien Jarno2010-02-091-1/+1
| | | | | | The store queues are located from 0xe0000000 to 0xe3ffffff. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: MMU: remove dead codeAurelien Jarno2010-02-091-18/+0
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-sh4: MMU: reduce the size of a TLB entryAurelien Jarno2010-02-091-12/+11
| | | | | | | Reduce the size of the TLB entry from 32 to 16 bytes, reorganising members and using a bit field. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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