summaryrefslogtreecommitdiffstats
path: root/target-sh4/translate.c
Commit message (Expand)AuthorAgeFilesLines
* tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson2013-09-021-1/+1
* cpu: Move singlestep_enabled field from CPU_COMMON to CPUStateAndreas Färber2013-07-231-3/+5
* target-sh4: Change gen_intermediate_code_internal() argument to SuperHCPUAndreas Färber2013-07-091-4/+5
* cpu: Turn cpu_dump_{state,statistics}() into CPUState hooksAndreas Färber2013-06-281-3/+4
* target-sh4: Introduce SuperHCPU subclassesAndreas Färber2013-03-121-84/+0
* gen-icount.h: Rename gen_icount_start/end to gen_tb_start/endPeter Maydell2013-03-031-2/+2
* target-sh4: Use mul*2 for dmul*Richard Henderson2013-02-231-28/+2
* target-sh4: Move TCG initialization to SuperHCPU initfnAndreas Färber2013-02-161-2/+1
* target-sh4: Introduce QOM realizefn for SuperHCPUAndreas Färber2013-02-161-2/+3
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-1/+1
* build: kill libdis, move disassemblers to disas/Paolo Bonzini2012-12-191-1/+1
* TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin2012-12-081-3/+3
* TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin2012-12-081-1/+1
* TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin2012-12-081-2/+2
* TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin2012-11-171-3/+3
* TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin2012-11-171-4/+4
* disas: avoid using cpu_single_envBlue Swirl2012-11-101-1/+1
* Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson2012-09-271-1/+1
* target-sh4: remove useless codeAurelien Jarno2012-09-211-4/+0
* target-sh4: cleanup DisasContextAurelien Jarno2012-09-211-30/+26
* target-sh4: rework exceptions handlingAurelien Jarno2012-09-211-6/+12
* target-sh4: remove gen_clr_t() and gen_set_t()Aurelien Jarno2012-09-211-13/+3
* target-sh4: optimize swap.wAurelien Jarno2012-09-211-11/+1
* target-sh4: optimize xtrctAurelien Jarno2012-09-211-1/+0
* target-sh4: implement addv and subv using TCGAurelien Jarno2012-09-211-2/+34
* target-sh4: implement addc and subc using TCGAurelien Jarno2012-09-211-2/+36
* target-sh4: switch to AREG0 free modeBlue Swirl2012-09-151-51/+63
* Kill off cpu_state_reset()Andreas Färber2012-06-041-5/+0
* target-sh4: Let cpu_sh4_init() return SuperHCPUAndreas Färber2012-06-041-2/+2
* target-sh4: Start QOM'ifying CPU initAndreas Färber2012-04-301-2/+0
* target-sh4: QOM'ify CPU resetAndreas Färber2012-04-301-20/+2
* target-sh4: QOM'ify CPUAndreas Färber2012-04-301-1/+3
* target-sh4: Don't overuse CPUStateAndreas Färber2012-03-141-23/+23
* Rename cpu_reset() to cpu_state_reset()Andreas Färber2012-03-141-2/+2
* target-sh4: Clean includesStefan Weil2012-02-281-6/+0
* target-sh4: ignore ocbp and ocbwb instructionsAurelien Jarno2012-01-101-11/+3
* target-sh4: Fix operands for fipr, ftrv instructionsStefan Weil2012-01-071-3/+3
* Use glib memory allocation and free functionsAnthony Liguori2011-08-201-1/+1
* Remove exec-all.h include directivesBlue Swirl2011-06-261-1/+0
* Remove unused function parameters from gen_pc_load and rename the functionStefan Weil2011-04-201-2/+1
* Fix conversions from pointer to tcg_target_longStefan Weil2011-04-101-1/+1
* target-sh4: fix negcAurelien Jarno2011-02-041-2/+2
* target-sh4: implement negc using TCGAurelien Jarno2011-01-161-1/+15
* target-sh4: use rotl/rotr when possibleAurelien Jarno2011-01-161-5/+3
* target-sh4: use setcond when possibleAurelien Jarno2011-01-141-29/+27
* target-sh4: log instructions start in TCG codeAurelien Jarno2011-01-141-0/+4
* target-sh4: simplify comparisons after a 'and' opAurelien Jarno2011-01-141-3/+3
* target-sh4: fix reset on r2dAurelien Jarno2011-01-141-12/+8
* target-sh4: optimize exceptionsAurelien Jarno2011-01-141-5/+0
* target-sh4: add ftrv instructionAurelien Jarno2011-01-141-0/+11
OpenPOWER on IntegriCloud