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* Rename target_phys_addr_t to hwaddrAvi Kivity2012-10-231-9/+9
* target-sh4: Don't overuse CPUStateAndreas Färber2012-03-141-14/+14
* Merge remote-tracking branch 'stefanha/trivial-patches' into stagingAnthony Liguori2011-12-051-1/+1
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| * fix spelling in target sub directoryDong Xu Wang2011-12-021-1/+1
* | sh_intc: convert interrupt controller to memory APIBenoît Canet2011-11-241-0/+3
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* Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl2011-08-071-2/+2
* Remove exec-all.h include directivesBlue Swirl2011-06-261-1/+0
* target-sh4: move intr_at_halt out of cpu_halted()Aurelien Jarno2011-03-031-2/+2
* target-sh4: update PTEH upon MMU exceptionAlexandre Courbot2011-01-261-0/+4
* sh4: implement missing mmaped TLB read functionsAurelien Jarno2011-01-261-0/+74
* sh4: implement missing mmaped TLB write functionsAurelien Jarno2011-01-261-1/+61
* target-sh4: fix index of address read error exceptionAlexandre Courbot2011-01-251-1/+1
* target-sh4: fix TLB invalidation codeAlexandre Courbot2011-01-251-2/+2
* target-sh4: correct use of ! and &Aurelien Jarno2011-01-151-2/+2
* target-sh4: improve TLBAurelien Jarno2011-01-101-21/+44
* target-sh4: implement writes to mmaped ITLBAurelien Jarno2011-01-091-0/+19
* Replace assert(0) with abort() or cpu_abort()Blue Swirl2010-03-181-3/+3
* Large page TLB flushPaul Brook2010-03-171-1/+2
* Remove cpu_get_phys_page_debug from userspace emulationPaul Brook2010-03-121-5/+0
* Fix incorrect exception_index useBlue Swirl2010-02-141-1/+1
* target-sh4: MMU: separate execute and read/write permissionsAurelien Jarno2010-02-091-21/+6
* target-sh4: MMU: fix store queue addressesAurelien Jarno2010-02-091-1/+1
* target-sh4: MMU: remove dead codeAurelien Jarno2010-02-091-18/+0
* target-sh4: MMU: optimize UTLB accessesAurelien Jarno2010-02-091-24/+14
* target-sh4: MMU: fix ITLB priviledge checkAurelien Jarno2010-02-091-1/+1
* target-sh4: MMU: simplify call to tlb_set_page()Aurelien Jarno2010-02-091-6/+3
* sh7750: handle MMUCR TI bitAurelien Jarno2010-02-091-0/+18
* Revert "Get rid of _t suffix"Anthony Liguori2009-10-011-3/+3
* Get rid of _t suffixmalc2009-10-011-3/+3
* Update to a hopefully more future proof FSF addressBlue Swirl2009-07-161-2/+1
* Include assert.h from qemu-common.hPaul Brook2009-05-131-1/+0
* SH: Fix linux-user _is_cached typo.edgar_igl2009-04-031-1/+1
* SH: Add cpu_sh4_is_cached for linux-user.edgar_igl2009-04-031-0/+6
* SH: Improve movca.l/ocbi emulation.edgar_igl2009-04-011-0/+44
* SH4: Fixed last UTLB unused and URB/URC managementaurel322009-03-031-1/+1
* SH4: Fixed last UTLB unusedaurel322009-03-031-1/+1
* SH4: Fixed last UTLB unusedaurel322009-03-031-1/+1
* clean build: Fix remaining sh4 warningsaurel322009-03-031-7/+7
* global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)aliguori2009-01-151-1/+1
* Convert references to logfile/loglevel to use qemu_log*() macrosaliguori2009-01-151-3/+3
* Update FSF address in GPL/LGPL boilerplateaurel322009-01-041-1/+1
* target-sh4: Add SH bit handling to TLBaurel322008-12-101-6/+6
* SH4: Eliminate P4 to A7 mangling (Takashi YOSHII).balrog2008-12-071-12/+0
* SH: On-chip PCI controller support (Takashi YOSHII).balrog2008-12-071-0/+3
* target-sh4: fix TLB/MMU emulationaurel322008-11-211-36/+29
* [sh4] MMU bug fixaurel322008-08-221-3/+20
* [sh4] memory mapped TLB entriesaurel322008-08-221-11/+111
* [sh4] delay slot bug fixaurel322008-08-221-0/+9
* [sh4] sleep instructionaurel322008-08-221-1/+2
* SH4 MMU improvementsaurel322008-05-091-6/+60
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