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* SH: Implement MOVCO.L and MOVLI.Laurel322009-03-021-0/+2
| | | | | | | | | | | * target-sh4/cpu.h (struct CPUSH4State): New field ldst. * target-sh4/translate.c (cpu_ldst): New. (sh4_translate_init): Initialize cpu_ldst. (_decode_opc): Support MOVCO.L and MOVLI.L. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6666 c046a42c-6fe2-441c-8c8c-71466251a162
* SH7750/51: add register BCR3, BCR4, PCR, RTCOR, RTCNT, RTCSR, SDMR2, SDMR3 ↵aurel322009-02-071-0/+1
| | | | | | | | | and fix BCR2 support Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6548 c046a42c-6fe2-441c-8c8c-71466251a162
* Update FSF address in GPL/LGPL boilerplateaurel322009-01-041-1/+1
| | | | | | | | | | The attached patch updates the FSF address in the GPL/LGPL boilerplate in most GPL/LGPLed files, and also in COPYING.LIB. Signed-off-by: Stuart Brady <stuart.brady@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: make the initial value of SR easier to readaurel322008-12-131-0/+4
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6016 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: add prefi, icbi, syncoaurel322008-12-131-0/+7
| | | | | | (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6013 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: add SH7785 as CPU optionaurel322008-12-131-0/+1
| | | | | | (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6012 c046a42c-6fe2-441c-8c8c-71466251a162
* target-sh4: remove 2 warningsaurel322008-12-111-0/+4
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5993 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: Implement FD bitaurel322008-12-071-1/+2
| | | | | | | | | | | | | | | | | | SH4 manual say that if a floating point instruction is executed while FD bit in the status register is 1, an exception should be raised. QEMU presently does not do that, so the kernel does not initialize FP state for any thread, nor does it save/restore FP state. The most apparent consequence is that while recent gcc/libc expect double-precision mode to be set by kernel, they run in single-precision mode, and all FP code produces wrong values. This patch fixes this. It also fixes a couple of places where PC was not updated before handling an exception, although both those places deal with invalid instruction and don't lead to any user-visible bugs. (Vladimir Prus) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5937 c046a42c-6fe2-441c-8c8c-71466251a162
* Refactor translation block CPU state handling (Jan Kiszka)aliguori2008-11-181-0/+11
| | | | | | | | | | | | | | | This patch refactors the way the CPU state is handled that is associated with a TB. The basic motivation is to move more arch specific code out of generic files. Specifically the long #ifdef clutter in tb_find_fast() has to be overcome in order to avoid duplicating it for the gdb watchpoint fixes (patch "Restore pc on watchpoint hits"). Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5736 c046a42c-6fe2-441c-8c8c-71466251a162
* Convert CPU_PC_FROM_TB to static inline (Jan Kiszka)aliguori2008-11-181-5/+7
| | | | | | | | | | | as macros should be avoided when possible. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
* qemu sh4 nptl supportaurel322008-09-151-0/+5
| | | | | | (Michael Trimarchi) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5223 c046a42c-6fe2-441c-8c8c-71466251a162
* sh4: CPU versioning.aurel322008-09-021-0/+17
| | | | | | | | | | | | | | | | | | | Trivial patch adding CPU listing and the ability to do per-subtype CVR/PVR/PRR values. Presently SH7750R and SH7751R definitions are provided, as these are the ones in present use in-tree. The CVR value for SH7751R is intentionally restricted so the kernel boots, though this will want to be switched to the proper CVR value once system emulation has sufficiently stabilized. This also makes it trivial to abstract subtype specific registers like MMU_PTEA and to set up feature bits in line with the kernel probing for things like conditionalizing FPU/DSP context. Signed-off-by: Paul Mundt <lethal@linux-sh.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5133 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: Remove dyngen leftoversaurel322008-09-011-3/+1
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5126 c046a42c-6fe2-441c-8c8c-71466251a162
* [sh4] memory mapped TLB entriesaurel322008-08-221-0/+2
| | | | | | | | | | | SH4 MMU's memory mapped TLB feature is implemented. SH-Linux seems to write to memory mapped TLB to invalidate a TLB entry, but does not to read it. So only memory write feature is implemented. Work on memory read feature is left. (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5067 c046a42c-6fe2-441c-8c8c-71466251a162
* [sh4] sleep instructionaurel322008-08-221-0/+1
| | | | | | | | This patch adds sleep instruction. (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5065 c046a42c-6fe2-441c-8c8c-71466251a162
* Move interrupt_request and user_mode_only to common cpu state.pbrook2008-07-011-2/+0
| | | | | | | | Save and restore env->interrupt_request and env->halted. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
* Add instruction counter.pbrook2008-06-291-0/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix typo.pbrook2008-05-301-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
* Move clone() register setup to target specific code. Handle fork-like clone.pbrook2008-05-301-0/+9
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
* Push common interrupt variables to cpu-defs.h (Glauber Costa)bellard2008-05-291-2/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
* moved halted field to CPU_COMMONbellard2008-05-281-1/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4 MMU improvementsaurel322008-05-091-0/+73
| | | | | | | (Shin-ichiro KAWASAKI) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4396 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4: system emulator interrupt update, by Magnus Damm.ths2007-12-021-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3762 c046a42c-6fe2-441c-8c8c-71466251a162
* SH4 delay slot code update, by Magnus Damm.ths2007-12-021-9/+9
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3761 c046a42c-6fe2-441c-8c8c-71466251a162
* added cpu_model parameter to cpu_init()bellard2007-11-101-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
* Replace is_user variable with mmu_idx in softmmu core,j_mayer2007-10-141-0/+11
| | | | | | | | | | | | | | allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
* find -type f | xargs sed -i 's/[\t ]$//g' # on most filesths2007-09-161-2/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
* Handle endianness of double floats, by Magnus Damm.ths2007-06-251-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3020 c046a42c-6fe2-441c-8c8c-71466251a162
* Emulate more fpu opcodes, by Magnus Damm.ths2007-06-221-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3002 c046a42c-6fe2-441c-8c8c-71466251a162
* Add missing cpu_halted function, by Magnus Damm.ths2007-06-221-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2998 c046a42c-6fe2-441c-8c8c-71466251a162
* Move target-specific defines to the target directories.ths2007-06-031-0/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2940 c046a42c-6fe2-441c-8c8c-71466251a162
* siginfo fix for Darwin/Mac OS X, by Pierre d'Herbemont.ths2007-01-311-3/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2369 c046a42c-6fe2-441c-8c8c-71466251a162
* Check ELF binaries for machine type and endianness.ths2006-12-231-0/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2274 c046a42c-6fe2-441c-8c8c-71466251a162
* SH bugfixes.pbrook2006-06-181-1/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1991 c046a42c-6fe2-441c-8c8c-71466251a162
* sh4 fmov et al instructions (amatus)bellard2006-06-141-0/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1971 c046a42c-6fe2-441c-8c8c-71466251a162
* sh4 target (Samuel Tardieu)bellard2006-04-271-0/+138
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1861 c046a42c-6fe2-441c-8c8c-71466251a162
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