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* Merge remote-tracking branch 'remotes/rth/tags/pull-tcg-20151007' into stagingPeter Maydell2015-10-081-58/+20
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do away with TB retranslation # gpg: Signature made Wed 07 Oct 2015 10:42:08 BST using RSA key ID 4DD0279B # gpg: Good signature from "Richard Henderson <rth7680@gmail.com>" # gpg: aka "Richard Henderson <rth@redhat.com>" # gpg: aka "Richard Henderson <rth@twiddle.net>" * remotes/rth/tags/pull-tcg-20151007: (26 commits) tcg: Adjust CODE_GEN_AVG_BLOCK_SIZE tcg: Check for overflow via highwater mark tcg: Allocate a guard page after code_gen_buffer tcg: Emit prologue to the beginning of code_gen_buffer tcg: Remove tcg_gen_code_search_pc tcg: Remove gen_intermediate_code_pc tcg: Save insn data and use it in cpu_restore_state_from_tb tcg: Pass data argument to restore_state_to_opc tcg: Add TCG_MAX_INSNS target-*: Drop cpu_gen_code define tcg: Merge cpu_gen_code into tb_gen_code target-sparc: Add npc state to insn_start target-sparc: Remove gen_opc_jump_pc target-sparc: Split out gen_branch_n target-sparc: Tidy gen_branch_a interface target-cris: Mirror gen_opc_pc into insn_start target-sh4: Add flags state to insn_start target-s390x: Add cc_op state to insn_start target-mips: Add delayed branch state to insn_start target-i386: Add cc_op state to insn_start ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-40/+4
| | | | | | | | | | | | | | | | | | | | It is no longer used, so tidy up everything reached by it. This includes the gen_opc_* arrays, the search_pc parameter and the inline gen_intermediate_code_internal functions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-4/+4
| | | | | | | | | | | | | | | | | | | | The gen_opc_* arrays are already redundant with the data stored in the insn_start arguments. Transition restore_state_to_opc to use data from the latter. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-0/+3
| | | | | | | | | | | | | | | | Adjust all translators to respect it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-s390x: Add cc_op state to insn_startRichard Henderson2015-10-071-1/+1
| | | | | | | | | | | | Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-*: Introduce and use cpu_breakpoint_testRichard Henderson2015-10-071-10/+6
| | | | | | | | | | | | | | | | | | | | | | | | Reduce the boilerplate required for each target. At the same time, move the test for breakpoint after calling tcg_gen_insn_start. Note that arm and aarch64 do not use cpu_breakpoint_test, but still move the inline test down after tcg_gen_insn_start. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-1/+2
| | | | | | | | | | | | | | | | This does tidy the icount test common to all targets. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-4/+2
| | | | | | | | | | | | | | | | | | | | While we're at it, emit the opcode adjacent to where we currently record data for search_pc. This puts gen_io_start et al on the "correct" side of the marker. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-071-1/+1
| | | | | | | | | | | | | | | | With an eye toward making it mandatory. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* | s390x/info registers: print vector registers properlyChristian Borntraeger2015-10-021-1/+1
|/ | | | | | | | | | | | | | | | | We want F12=0000000000000000 F13=0000000000000000 F14=0000000000000000 F15=0000000000000000 V00=00000000000000000000000000000000 V01=00000000000000000000000000000000 instead of F12=0000000000000000 F13=0000000000000000 F14=0000000000000000 F15=0000000000000000 V00=00000000000000000000000000000000 V01=00000000000000000000000000000000 V02=00000000000000000000000000000000 Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com> Signed-off-by: Jens Freimann <jfrei@linux.vnet.ibm.com> Message-Id: <1443689387-34473-5-git-send-email-jfrei@linux.vnet.ibm.com> Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
* tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson2015-08-241-15/+15
| | | | | | Replacing it with tcg_gen_extrl_i64_i32. Signed-off-by: Richard Henderson <rth@twiddle.net>
* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | disas does not need to access the CPU env for any reason. Change the APIs to accept CPU pointers instead. Small change pattern needs to be applied to all target translate.c. This brings us closer to making disas.o a common-obj and less architecture specific in general. Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Luiz Capitulino <lcapitulino@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
* target-s390x: PER: add Breaking-Event-Address registerAurelien Jarno2015-06-171-6/+23
| | | | | | | | | | | | | This patch adds support for PER Breaking-Event-Address register. Like real hardware, it save the current PSW address when the PSW address is changed by an instruction. We have to take care of optimizations QEMU does, a branch to the next instruction is still a branch. This register is copied to low core memory when a program exception happens. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: PER instruction-fetch event supportAurelien Jarno2015-06-171-0/+8
| | | | | | | | | | | | | | | | | | | For the PER instruction-fetch, we can't use the QEMU breakpoint infrastructure as it triggers for a single address and not a full address range, and as it actually stop before the instruction and not before. We therefore call an helper with the just fetched instruction address, which check if the address is within the PER address range. If it is the case, an event is recorded and will be signaled through an exception. Note that we implement here the PER-3 behaviour, that is an invalid opcode is not considered as an instruction fetch. Without PER-3 this behavious is undefined. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: PER successful-branching event supportAurelien Jarno2015-06-171-0/+39
| | | | | | | | | | | | | For the PER successful-branching event support, we can't rely on any QEMU infrastucture. We therefore call an helper in all places where a branch can be taken. We have to pay attention to the branch to next case, as it's still a taken branch. We don't need to care about the cases using goto_tb, as we have disabled them in the previous patch. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: basic PER event handlingAurelien Jarno2015-06-171-1/+17
| | | | | | | | | | | | | | | | | | This patch add basic support to generate PER exceptions. It adds two fields to the cpu structure to record for the PER address and PER code & ATMID values. When an exception is triggered and a PER event is pending, the two PER values are copied to the lowcore area. At the end of an instruction, an helper is checking for a possible pending PER event and triggers an exception in that case. For that to work with branches, we need to disable TB chaining when PER is activated. Fortunately it's already in the TB flags. Finally in case of a SERVICE CALL exception, we need to trigger the PER exception immediately after. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: wire up I/O instructions in TCG modeAlexander Graf2015-06-171-3/+95
| | | | | | | | | The code handling the I/O instructions for KVM decodes the instruction itself. In TCG mode also pass the full instruction word to the helpers. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: wire up DIAG IPL in TCG modeAurelien Jarno2015-06-171-6/+10
| | | | | | | | | | | | | | DIAG IPL is already implemented for KVM, but not wired from TCG. For that change the format of the instruction so that we can get R1 and R3 numbers in addition to the function code. The diag function can change plenty of things, including CC, so we should enter with a static CC. Also it doesn't set the value of general register 2 to 0 as in the current code. We also need to exit the CPU loop after a reset, which means a new PSW. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: implement high-word facilityAurelien Jarno2015-06-051-0/+51
| | | | | | | | | Besides RISBHG and RISBLG, all high-word instructions are not implemented. Fix that. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: implement load-and-trap facilityAurelien Jarno2015-06-051-9/+71
| | | | | | | | | | | At the same time move the trap code from op_ct into gen_trap and use it for all new functions. The value needs to be stored back to register before the exception, but also before the brcond (as we don't use temp locals). That's why we can't use wout helper. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: implement miscellaneous-instruction-extensions facilityAurelien Jarno2015-06-051-0/+1
| | | | | | | | | | RISBGN is the same as RISBG, but without setting the condition code. CLT and CLGT are the same as CLRT and CLGRT, but using memory for the second operand. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: implement TRANSLATE EXTENDED instructionAurelien Jarno2015-06-051-0/+9
| | | | | | | | It is part of the basic zArchitecture instructions. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: implement TRANSLATE AND TEST instructionAurelien Jarno2015-06-051-0/+10
| | | | | | | | | It is part of the basic zArchitecture instructions. Allow it to be call from EXECUTE. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: implement LOAD FP INTEGER instructionsAurelien Jarno2015-06-051-0/+25
| | | | | | | | | This is needed to pass the gcc.c-torture/execute/ieee/20010114-2.c test in the gcc testsuite. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: fix exception for invalid operation codeAurelien Jarno2015-06-051-1/+1
| | | | | | | | | | | | | | When an operation code is not recognized (ie invalid instruction) an operation exception should be generated instead of a specification exception. The latter is for valid opcode, with invalid operands or modifiers. This give a very basic GDB support in the guest, as it uses the invalid opcode 0x0001 to generate a trap. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: implement LAY and LAEY instructionsAurelien Jarno2015-06-051-0/+35
| | | | | | | | This complete the general-instructions-extension facility, enable it. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [agraf: remove facility bit] Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: fix LOAD MULTIPLE instruction on page boundaryAurelien Jarno2015-06-051-29/+99
| | | | | | | | | | | | | | | | | | | | When consecutive memory locations are on page boundary a page fault might occur when using the LOAD MULTIPLE instruction. In that case real hardware doesn't load any register. This is an important detail in case the base register is in the list of registers to be loaded. If a page fault occurs this register might be overwritten and when the instruction is later restarted the wrong base register value is useD. Fix this by first loading the first and last value from memory, hence triggering all possible page faults, and then the remaining registers. This fixes random segmentation faults seen in the guest. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: optimize (negative-) abs computationAurelien Jarno2015-06-051-2/+14
| | | | | | | | | Now that movcond exists, it's easy to write (negative-) absolute value using TCG code instead of an helper. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-s390x: fix CC computation for EX instructionAurelien Jarno2015-06-051-2/+1
| | | | | | | | | | | | | | | Commit 7a6c7067f optimized CC computation by only saving cc_op before calling helpers as they either don't touch the CC or generate a new static value. This however doesn't work for the EX instruction as the helper changes or not the CC value depending on the actual executed instruction (e.g. MVC vs CLC). This patches force a CC computation before calling the helper. This fixes random memory corruption occuring in guests. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> [agraf: remove set_cc_static in op_ex as suggested by rth] Signed-off-by: Alexander Graf <agraf@suse.de>
* s390x: Add vector registers to HMP outputEric Farman2015-05-271-0/+6
| | | | | | | | | | | There are mechanisms to dump registers via the qemu HMP interface, such as the "info registers" command. Expand this output to dump the new vector registers. Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
* s390x: Vector Register IOCTLsEric Farman2015-05-271-1/+1
| | | | | | | | | | | | | | | | Handle the actual syncing of the vector registers with kernel space, via the get/put register IOCTLs. The vector registers that were introduced with the z13 overlay the existing floating point registers. FP registers 0-15 are the high-halves of vector registers 0-15. Thus, remove the freg fields and replace them with the equivalent vector field to avoid errors in duplication. Moreover, synchronize either the vector registers via kvm_sync_regs, or floating point registers via the GET/SET FPU IOCTLs. Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
* s390x: Common access to floating point registersEric Farman2015-05-271-1/+1
| | | | | | | | | | Provide a routine to access the correct floating point register, to simplify future expansion. Suggested-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Eric Farman <farman@linux.vnet.ibm.com> Reviewed-by: David Hildenbrand <dahi@linux.vnet.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
* s390x: Add interlocked access facility 1 instructionsAlexander Graf2015-05-131-0/+35
| | | | | | | | | We're currently missing all instructions defined by the "interlocked-access facility 1" which is part of zEC12. This patch implements all of them except for LPD and LPDG. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* s390x: Fix stoc directionAlexander Graf2015-05-131-0/+4
| | | | | | | | | | | The store conditional instruction wants to store when the condition is fulfilled, so we should branch out when it's not true. The code today branches out when the condition is true, clearly reversing the logic. Fix it up by negating the condition. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* misc: Fix new collection of typosStefan Weil2015-04-301-1/+1
| | | | | | | | | | All of them were reported by codespell. Most typos are in comments, one is in an error message. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | This is improved type checking for the translators -- it's no longer possible to accidentally swap arguments to the branch functions. Note that the code generating backends still manipulate labels as int. With notable exceptions, the scope of the change is just a few lines for each target, so it's not worth building extra machinery to do this change in per-target increments. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-121-6/+3
| | | | | | | | The method by which we count the number of ops emitted is going to change. Abstract that away into some inlines. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-121-1/+1
| | | | | Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-s390x: Mark check_privileged() as !CONFIG_USER_ONLYPeter Maydell2015-02-031-1/+3
| | | | | | | | | | | | | | The function check_privileged() is only used in the softmmu configs; wrap it in an #ifndef CONFIG_USER_ONLY to avoid clang warnings on the linux-user builds. [rth: Remove inline marker too; it was only there to prevent exactly this warning in GCC.] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Stefan Weil <sw@weilnetz.de> Message-id: 1419373100-17690-2-git-send-email-peter.maydell@linaro.org Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-s390: Implement ECAGRichard Henderson2015-02-031-0/+7
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-s390: Implement LURA, LURAG, STURGRichard Henderson2015-02-031-0/+26
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-s390: Fix STIDPRichard Henderson2015-02-031-0/+6
| | | | | | | | The implementation had been incomplete, as we did not store the machine type. Note that the machine_type member is still unset during initialization, so this has no effect yet. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-s390: Implement EPSWRichard Henderson2015-02-031-0/+18
| | | | Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-s390: Implement SAM specification exceptionRichard Henderson2015-02-031-4/+27
| | | | | | | Also, these are user-mode instructions; allow their use in CONFIG_USER_ONLY. Signed-off-by: Richard Henderson <rth@twiddle.net>
* gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
| | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* s390x: Implement SAM{24,31,64}Alexander Graf2014-11-051-0/+12
| | | | | | | | | | | | | | | | The SAM instructions simply change 2 bits in PSW.MASK to advertise the current memory mode. While we can't fully guarantee that 31 bit mode (or even remotely 24 bit mode) actually work correctly, we don't check whether lpswe modifies these bits, so we shouldn't keep the guest from executing SAM instructions either. This patch implements all SAM instrutions with their actual PSW changing semantics, making more recent Linux kernels boot properly which do issue a SAM31 call during early boot. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>
* trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova2014-08-121-0/+2
| | | | | Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* target-s390x: Remove unused ld_code6() functionPeter Maydell2014-06-241-5/+0
| | | | | | | | The ld_code6() function is unused; remove it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-051-0/+1
| | | | | | | | | | This will collect all load and store helpers soon. For now it is just a replacement for softmmu_exec.h, which this patch stops including directly, but we also include it where this will be necessary in order to simplify the next patch. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-281-3/+2
| | | | | | | | | | Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
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