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* PPC: KVM: Make pv hcall endian agnosticAlexander Graf2014-06-161-8/+8
| | | | | | | | | | | | | | | | There were a few revisions of the Linux kernel that incorrectly swapped the hcall instructions when they saw ePAPR compliant hypercalls. We already have fixups for those in place when running with PR KVM, but HV KVM and systems that don't implement hypercalls at all are still broken because they fall back to the QEMU implementation of fallback hypercalls. So let's make the fallback hypercall instruction path endian agnostic. This only really works well for 64bit guests, but I don't think there are any 32bit systems left that don't implement real pv hcall support, so we'll never get into this code path. Signed-off-by: Alexander Graf <agraf@suse.de>
* powerpc: use float64 for frsqrteTristan Gingold2014-06-161-3/+0
| | | | | | | | | | | | | Remove the code that reduce the result to float32 as the frsqrte instruction is defined to return a double-precision estimate of the reciprocal square root. Although reducing the fractional part is harmless (as the estimation must have at least 12 bits of precision according to the old PEM), reducing the exponent range is not correct. Signed-off-by: Tristan Gingold <gingold@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODEAlexey Kardashevskiy2014-06-162-3/+8
| | | | | | | | | | | | | | | This adds handling of the RESOURCE_ADDR_TRANS_MODE resource from the H_SET_MODE, for POWER8 (PowerISA 2.07) only. This defines AIL flags for LPCR special register. This changes @excp_prefix according to the mode, takes effect in TCG. This turns support of a new capability PPC2_ISA207S flag for TCG. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Enable DABRX SPR and limit it to <=POWER7Alexey Kardashevskiy2014-06-161-1/+14
| | | | | | | | | | | This adds DABRX SPR. As DABR(X) are present in POWER CPUs till POWER7 only and POWER8 does not have them (as it implements more powerful facility instead), this limits DABR/DABRX registration by POWER7 (inclusive). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Enable PPR and VRSAVE SPRs migrationAlexey Kardashevskiy2014-06-161-8/+8
| | | | | | | | | This hooks SPR with their "KVM set_one_reg" counterparts which enables their migration. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add POWER8's Event Based Branch (EBB) control SPRsAlexey Kardashevskiy2014-06-162-0/+64
| | | | | | | | | | | | POWER8 supports Event-Based Branch Facility (EBB). It is controlled via set of SPRs access to which should generate an "Facility Unavailable" interrupt if the facilities are not enabled in FSCR for problem state. This adds EBB SPRs. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* KVM: target-ppc: Enable TM state migrationAlexey Kardashevskiy2014-06-163-0/+87
| | | | | | | | | This adds migration support for registers saved before Transactional Memory (TM) transaction started. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add POWER8's TM SPRsAlexey Kardashevskiy2014-06-164-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | This adds TM (Transactional Memory) SPRs. This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to handle upper half SPRs such as TEXASRU which is upper half of TEXASR. Since this is not the only register like that and their numbers go consequently, it makes sense to generalize the helpers. This adds a gen_msr_facility_check() helper which purpose is to generate the Facility Unavailable exception if the facility is disabled. It is a copy of gen_fscr_facility_check() but it checks for enabled facility in MSR rather than FSCR/HFSCR. It still sets the interrupt cause in FSCR/HFSCR (whichever is passed to the helper). This adds spr_read_tm/spr_write_tm/spr_read_tm_upper32/spr_write_tm_upper32 which are used for TM SPRs. This adds TM-relates MSR bits definitions. This enables TM in POWER8 CPU class' msr_mask. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add POWER8's MMCR2/MMCRS SPRsAlexey Kardashevskiy2014-06-162-0/+25
| | | | | | | | This adds POWER8 specific PMU MMCR2/MMCRS SPRs. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Enable FSCR facility check for TARAlexey Kardashevskiy2014-06-161-2/+34
| | | | | | | | | | | | | | | This makes user-privileged read/write fail if TAR facility is not enabled in FSCR. Since this is the very first check for enabled in FSCR facility, this also adds gen_fscr_facility_check() for using in spr_write_tar()/ spr_read_tar(). This enables TAR in FSCR for user mode unconditionally. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add POWER8's FSCR SPRAlexey Kardashevskiy2014-06-166-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | This adds an FSCR (Facility Status and Control Register) SPR. This defines names for FSCR bits. This defines new exception type - POWERPC_EXCP_FU - "facility unavailable" (FU). This registers an interrupt vector for it at 0xF60 as PowerISA defines. This adds a TCG helper_fscr_facility_check() helper to raise an exception if the facility is not enabled. It updates the interrupt cause field in FSCR. This adds a TCG translation block generation code. The helper may be used for HFSCR too as it has the same format. The helper raising FU exceptions is not used by this patch but will be in the next ones. This adds gen_update_current_nip() to update NIP in DisasContext. This helper is not used now and will be called before checking for a condition for throwing an FU exception. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add POWER8's TIR SPRAlexey Kardashevskiy2014-06-162-0/+11
| | | | | | | | | This adds TIR (Thread Identification Register) SPR first defined for server CPUs in PowerISA 2.07. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Refactor class init for POWER7/8Alexey Kardashevskiy2014-06-161-39/+61
| | | | | | | | This extends init_proc_book3s_64 to support POWER7 and POWER8. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Switch POWER7/8 classes to use correct PMU SPRsAlexey Kardashevskiy2014-06-161-15/+2
| | | | | | | | | | | | | | | This replaces gen_spr_7xx() call (which registers 32bit SPRs) with gen_spr_book3s_pmu() call. This removes SPR_7XX_PMC5/6 as they are for 32bit and gen_spr_book3s_pmu() already registers correct PMC5/6 SPRs. This removes explicit MMCRA registration as gen_spr_book3s_pmu() does it anyway. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Make use of gen_spr_power5p_lpar() for POWER7/8Alexey Kardashevskiy2014-06-161-5/+1
| | | | | | | | This makes use of generic gen_spr_power5p_lpar() which registers LPCR SPR. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Make use of gen_spr_book3s_altivec() for POWER7/8Alexey Kardashevskiy2014-06-161-7/+1
| | | | | | | | | | This replaces VRSAVE registration and vscr_init() call with gen_spr_book3s_altivec() which is generic and does the same thing if insns_flags has PPC_ALTIVEC bit set (which POWER7/8 have set). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Move POWER7/8 CFAR/DSCR/CTRL/PPR/PCR SPR registration to helpersAlexey Kardashevskiy2014-06-161-30/+40
| | | | | | | | | | | | | This moves SCFAR/DSCR/CTRL/PPR/PCR PRs to helpers. Later these helpers will be called from generalized init_proc_book3s_64(). This switches init_proc_POWER7() to use generalized gen_spr_book3s_common() which registers CRTL SPR under slightly different names. No change in behaviour or non-debug output is expected. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Move POWER8 TCE Address control (TAR) to a helperAlexey Kardashevskiy2014-06-161-5/+9
| | | | | | | | | This moves TAR SPR to a helper. Later this helper will be called from generalized init_proc_book3s_64(). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Move POWER7/8 PIR/PURR/SPURR SPR registration to helpersAlexey Kardashevskiy2014-06-161-14/+26
| | | | | | | | | This moves PIR/PURR/SPURR SPRs to helpers. Later these helpers will be called from generalized init_proc_book3s_64(). Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Enable PMU SPRs migrationAlexey Kardashevskiy2014-06-161-52/+52
| | | | | | | | | This enabled PMU SPRs migration by hooking hypv privileged versions with "KVM one reg" IDs. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Remove check_pow_970FXAlexey Kardashevskiy2014-06-161-9/+1
| | | | | | | | | | After merging 970s into one class, check_pow_970() is used for all of them. Since POWER5+ is no different in the matter of supported power modes, let's use the same check_pow() callback for POWER5+ too, Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Introduce and reuse generalized init_proc_book3s_64()Alexey Kardashevskiy2014-06-161-58/+27
| | | | | | | | | | | | | | | | | | | | | | | | At the moment every POWER CPU family has its own init_proc_POWERX function. E500 already has common init function so we try to do the same thing. This introduces BOOK3S_CPU_TYPE enum with 2 values - 970 and POWER5+. This introduces generalized init_proc_book3s_64() which accepts a CPU type as a parameter. This uses new init function for 970 and POWER5+ CPU classes. 970 and POWER5+ use the same CPU class initialization except 3 things: 1. logical partitioning is controlled by LPCR (POWER5+) and HID4 (970) SPRs; 2. 970 does not have EAR (External Access Register) SPR and PowerISA 2.03 defines one so keep it only for POWER5+; 3. POWER5+ does not have ALTIVEC so insns_flags does not have PPC_ALTIVEC flag set and gen_spr_book3s_altivec() won't init ALTIVEC for POWER5+. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add HID4 SPR for PPC970Alexey Kardashevskiy2014-06-162-0/+12
| | | | | | | | | Previously LPCR was registered for the 970 class which was wrong as it does not have LPCR. Instead, HID4 is used which this patch registers. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add PMC7/8 to 970 classAlexey Kardashevskiy2014-06-162-0/+30
| | | | | | | | | | | Compared to PowerISA-compliant CPUs, 970 family has most of them plus PMC7/8 which are only present on 970 but not on POWER5 and later CPUs. Since we are changing SPRs for Book3s/970 families, let's add them too. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add PMC5/6, SDAR and MMCRA to 970 familyAlexey Kardashevskiy2014-06-161-0/+32
| | | | | | | | | | | | | MMCR0, MMCR1, MMCRA, PMC1..6, SIAR, SDAR are defined for 970 and PowerISA CPUs. Since we are building common infrastructure for SPRs intialization to share it between 970 and POWER5+/7/..., let's add missing SPRs to the 970 family. Later rework of CPU class initialization will use those for all PowerISA CPUs. This adds new SPRs and enables writing to Uxxxx SPRs from supermode. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add "POWER" prefix to MMCRA PMU registersAlexey Kardashevskiy2014-06-162-2/+3
| | | | | | | | | Since we started adding "POWER" prefix to 64bit PMU SPRs, let's finish the transition and fix MMCRA and define a supermode version of it. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Copy and split gen_spr_7xx() for 970Alexey Kardashevskiy2014-06-162-1/+125
| | | | | | | | | | | | | | | | | | | | | | | | This stops using 7xx common SPRs init function and adds separate set of helpers for 970. This does not copy ICTC SPR as neither 970 manual nor PowerISA mention it. This defines 970/book3s PMU SPRs constants as they differs from the ones used for 7XX. This creates 2 helpers for PMU SPRs, one for supermode privileged SPRs and one for user privileged SPRs as "sup" versions can be shared across the family while "user" versions will behave different starting POWER8 (which will be addressed later). This allows writing to Uxxxx SPRs from supermode. spr_write_ureg() is implemented for this as a copy of already existing spr_read_ureg(). This allows writing to supervisor's SIAR - it used to be disabled when gen_spr_7xx() was used. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Make UCTRL a mirror of CTRLAlexey Kardashevskiy2014-06-161-2/+2
| | | | | | | | | | This changes UCTRL SPR to read from its supermode copy. This enables reading from UCTRL in user mode. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Refactor PPC970Alexey Kardashevskiy2014-06-161-13/+32
| | | | | | | | | | This splits one init_proc_970() into a set of small helpers. Later init_proc_970() will be generalized and will call different set of helpers depending on the current CPU class. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Merge 970FX and 970MP into a single 970 classAlexey Kardashevskiy2014-06-163-205/+20
| | | | | | | | | | | | | | | | | | | | | | | The differences between classes were: 1. SLB size, was 32 for 970 and 64 for others, should be 64 for all; 2. check_pow() callback, HID0 format is the same so should be the same 0x01C00000 which means "deep nap", "doze" and "nap" bits set; 3. LPCR - 970 does not have it but 970MP had one (by mistake). This fixes wrong differences and makes one 970 class. This fixes wrong registration of LPCR which is not present on 970. This defines HID0 bits and uses them in check_pow_970(). This does not copy MSR_SHV (Hypervisor State, HV) bit from 970FX to 970 class as we do not emulate hypervisor in QEMU anyway. This does not remove check_pow_970FX now as it is still used by POWER5+ class, this will be addressed later. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRsAlexey Kardashevskiy2014-06-162-69/+69
| | | | | | | | | | | | | As defined in Linux kernel, PMC*, SIAR, MMCR0/1 have different numbers for 32 and 64 bit POWERPC. We are going to support 64bit versions too so let's rename 32bit ones to avoid confusion. This is a mechanical patch so it does not fix obvious mistake with these registers in POWER7 yet, this will be fixed later. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Fix Temporary Variable Leak in bctarTom Musta2014-06-161-1/+1
| | | | | | | | | Fix a temporary variable leak detected in the bctar instruction: Opcode 13 10 11 (4d910460) leaked temporaries Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: e500: Merge 32 and 64 bit SPE emulationAlexander Graf2014-06-162-583/+132
| | | | | | | | | | | | | | | | | | | | | Today we have a lot of conditional code in the SPE emulation depending on whether we have 64bit GPRs or not. Unfortunately the assumption that we can just recycle the 64bit GPR implementation is wrong. Normal SPE implementations maintain the upper 32 bits on all non-SPE instructions which then only modify the low 32 bits. However all instructions we model that adhere to the normal SF based switching don't care whether they operate on 32 or 64 bit registers and just always use the full 64 bits. So let's remove that dubious SPE optimization and revert everything to the same code path the 32bit target code was taking. That way we get rid of differences between the two implementations, but will get a slight performance hit when emulating SPE instructions. This fixes SPE emulation with qemu-system-ppc64 for me. Signed-off-by: Alexander Graf <agraf@suse.de>
* KVM: PPC: Expose fixup hcall capabilityAlexander Graf2014-06-162-0/+13
| | | | | | | New kvm versions expose a PPC_FIXUP_HCALL capability. Make it visible to machine code so we can take decisions based on it. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: SPE: Fix high-bits bitmaskAlexander Graf2014-06-161-2/+2
| | | | | | | | | | The SPE emulation code wants to access the highest 32bits of a 64bit register and uses the andi TCG instruction for that. Unfortunately it masked with the wrong mask. Fix the mask to actually cover the upper 32 bits. This fixes simple multiplication tests with SPE guests for me. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: e500: Fix TLB lookup for 32bit CPUsAlexander Graf2014-06-161-0/+5
| | | | | | | | | | | | | When we run 32bit guest CPUs (or 32bit guest code on 64bit CPUs) on qemu-system-ppc64 the TLB lookup will use the full effective address as pointer. However, only the first 32bits are valid when MSR.CM = 0. Check for that condition. This makes QEMU boot an e500v2 guest with more than 1G of RAM for me. Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Support VSX in PPC User ModeTom Musta2014-06-161-0/+1
| | | | | | | | Some modern tool chains use VSX instructions. Therefore attempt to enable the VSX MSR bit by default, just like similar bits (FP, VEC, SPE, etc.). Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Allow little-endian user mode.Doug Kwan2014-06-163-95/+85
| | | | | | | | | This allows running PPC64 little-endian in user mode if target is configured that way. In PPC64 LE user mode we set MSR.LE during initialization. Signed-off-by: Doug Kwan <dougkwan@google.com> Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: e500: Fix MMUCSR0 emulationAlex Zuepke2014-06-163-5/+3
| | | | | | | | | | A "mtspr SPRMMUCSR0, reg" always flushed TLB0, because it passed the SPR number 0x3f4 to the flush routine. But we want to flush either TLB0 or TBL1 depending on the GPR value. Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de> [agraf: change subject line, fix TCGv size mismatch] Signed-off-by: Alexander Graf <agraf@suse.de>
* spapr_iommu: Get rid of window_size in sPAPRTCETableAlexey Kardashevskiy2014-06-162-3/+3
| | | | | | | | | | | | | | This removes window_size as it is basically a copy of nb_table shifted by SPAPR_TCE_PAGE_SHIFT. As new dynamic DMA windows are going to support windows as big as the entire RAM and this number will be bigger that 32 capacity, we will have to do something about @window_size anyway and removal seems to be the right way to go. This removes dma_window_start/dma_window_size from sPAPRPHBState as they are no longer used. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* spapr_iommu: Enable multiple TCE requestsAlexey Kardashevskiy2014-06-162-0/+13
| | | | | | | | | | | | | | | Currently only single TCE entry per request is supported (H_PUT_TCE). However PAPR+ specification allows multiple entry requests such as H_PUT_TCE_INDIRECT and H_STUFF_TCE. Having less transitions to the host kernel via ioctls, support of these calls can accelerate IOMMU operations. This implements H_STUFF_TCE and H_PUT_TCE_INDIRECT. This advertises "multi-tce" capability to the guest if the host kernel supports it (KVM_CAP_SPAPR_MULTITCE) or guest is running in TCG mode. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Fix popcntb Opcode BugTom Musta2014-06-161-1/+1
| | | | | | | | | The popcntb instruction is erroneously encoded with opcode extension (opc1,opc2) = (0x03,0x03). Bits 21-30 of popcntb are 122 = 0b00011-0b11010 and therefore this should be encoded as (opc1,opc2) = (0x1A, 0x03). Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* KVM: PPC: Enable compatibility modeAlexey Kardashevskiy2014-06-163-0/+16
| | | | | | | | | | | | The host kernel implements a KVM_REG_PPC_ARCH_COMPAT register which this uses to enable a compatibility mode if any chosen. This sets the KVM_REG_PPC_ARCH_COMPAT register in KVM. ppc_set_compat() signals the caller if the mode cannot be enabled by the host kernel. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: fix TCG compat setting] Signed-off-by: Alexander Graf <agraf@suse.de>
* spapr: Limit threads per core according to current compatibility modeAlexey Kardashevskiy2014-06-162-0/+28
| | | | | | | | | | | | | | | | | | This puts a limit to the number of threads per core based on the current compatibility mode. Although PowerISA specs do not specify the maximum threads per core number, the linux guest still expects that PowerISA2.05-compatible CPU supports only 2 threads per core as this is what POWER6 (2.05 compliant CPU) implements, the same is for POWER7 (2.06, 4 threads) and POWER8 (2.07, 8 threads). This calls spapr_fixup_cpu_smt_dt() with the maximum allowed number of threads which affects ibm,ppc-interrupt-server#s and ibm,ppc-interrupt-gserver#s properties. The number of CPU nodesremains unchanged. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Define Processor Compatibility MasksAlexey Kardashevskiy2014-06-162-0/+4
| | | | | | | | This introduces PCR mask for supported compatibility modes. This will be used later by the ibm,client-architecture-support call. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Implement "compat" CPU optionAlexey Kardashevskiy2014-06-163-0/+47
| | | | | | | | | | | | | | | | | | | This adds basic support for the "compat" CPU option. By specifying the compat property, the user can manually switch guest CPU mode from "raw" to "architected". This defines feature disable bits which are not used yet as, for example, PowerISA 2.07 says if 2.06 mode is selected, the TM bit does not matter - transactional memory (TM) will be disabled because 2.06 does not define it at all. The same is true for VSX and 2.05 mode. So just setting a mode must be ok. This does not change the existing behavior as the actual compatibility mode support is coming in next patches. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: fix compilation on 32bit hosts] Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add "compat" CPU optionAlexey Kardashevskiy2014-06-163-0/+87
| | | | | | | | | | | | | | | | | | PowerISA defines a compatibility mode for server POWERPC CPUs which is supported by the PCR special register which is hypervisor privileged. To support this mode for guests, SPAPR defines a set of virtual PVRs, one per PowerISA spec version. When a hypervisor needs a guest to work in a compatibility mode, it puts a virtual PVR value into @cpu-version property of a CPU node. This introduces a "compat" CPU option which defines maximal compatibility mode enabled. The supported modes are power6/power7/power8. This does not change the existing behaviour, new property will be used by next patches. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Set the correct endianness in ELF dump headerBharata B Rao2014-06-161-4/+8
| | | | | | | Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Introduce callback for interrupt endiannessGreg Kurz2014-06-162-0/+17
| | | | | | | | | | | | | | | POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR special purpose register to decide the endianness to use when entering interrupt handlers. When running a Linux guest, this provides a hint on the endianness used by the kernel. And when it comes to dumping a guest, the information is needed to write ELF headers using the kernel endianness. Suggested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> [agraf: change subject line] Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Support dump for little endian ppc64Bharata B Rao2014-06-161-33/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix ppc64 arch specific dump code to support all combinations of little/big endian hosts/guests. FWIW the current code is broken for altivec registers when guest and host have a different endianness: these 128-bit registers are written to guest memory as a two 64-bit entities and we should also swap them. Unit testing was done with the following program provided by Tom Musta: #include <stdio.h> #include <stdint.h> #include <stdlib.h> int main(int argc, char** argv) { __uint128_t v = ((__uint128_t)0x0001020304050607ull << 64) | 0x08090a0b0c0d0e0full; register void * vptr asm ("r11"); vptr = &v; for(;;) asm volatile ("lvx 30,0,11" ); } When sending SIGABRT to this program and examining the core file, we get: - ppc64 : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64le: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We expect to find the very same layout in the QEMU dump since they are real core files. This is what we get: - ppc64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - ppc64 host, ppc64le guest : 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 - x86_64 host, ppc64 guest : 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f - x86_64 host, ppc64le guest: 0f 0e 0d 0c 0b 0a 09 08 07 06 05 04 03 02 01 00 We introduce a NoteFuncArg type to avoid adding extra arguments to all note functions. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> [ rebased on top of current master branch, introduced NoteFuncArg, use new cpu_to_dump{16,32,64} endian helpers, fix altivec support, Greg Kurz <gkurz@linux.vnet.ibm.com> ] Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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