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* cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signalNathan Froyd2009-08-241-0/+1
| | | | | | | | | | | | | | | handle_cpu_signal is very nearly copy-paste code for each target, with a few minor variations. This patch sets up appropriate defaults for a generic handle_cpu_signal and provides overrides for particular targets that did things differently. Fixing things like the persistent (XXX: use sigsetjmp) should now become somewhat easier. Previous comments on this patch suggest that the "activate soft MMU for this block" comments refer to defunct functionality. I have removed such blocks for the appropriate targets in this patch. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Replace REGX with PRIx64Blue Swirl2009-08-163-5/+4
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plxBlue Swirl2009-08-165-174/+173
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Replace always_inline with inlineBlue Swirl2009-08-166-285/+278
| | | | | | We define inline as always_inline. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-ppc: add exceptions for conditional storesNathan Froyd2009-08-032-20/+56
| | | | | Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: malc <av1474@comtv.ru>
* target-ppc: retain l{w,d}arx loaded valueNathan Froyd2009-08-035-10/+17
| | | | | | | | | We do this so we can check on the corresponding stc{w,d}x. whether the value has changed. It's a poor man's form of implementing atomic operations and is valid only for NPTL usermode Linux emulation. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: malc <av1474@comtv.ru>
* target-ppc: add cpu_set_tlsNathan Froyd2009-08-031-0/+11
| | | | | Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: malc <av1474@comtv.ru>
* target-ppc: fix cpu_clone_regsNathan Froyd2009-08-031-3/+1
| | | | | | | | We only need to make sure that the clone syscall looks like it succeeded, not clobber 60% of the register set. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: malc <av1474@comtv.ru>
* rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIANJuan Quintela2009-07-273-19/+19
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Rename HAVE_FDT to CONFIG_FDT and define it also in MakefileJuan Quintela2009-07-271-1/+1
| | | | | Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Use correct input constantAlexander Graf2009-07-221-1/+9
| | | | | | | | | 440 and desktop codes use different input constants for interrupt indication. Let's use the respective ones for KVM. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Set PVR in sregsAlexander Graf2009-07-221-1/+7
| | | | | | | | | | | We need to tell the kernel about some initial CPU state we don't have yet, so let's use the "sregs" IOCTL for that and simply put the Processor Version Register in there. Now the kernel knows which guest CPU to virtualize. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Fix most warnings (errors with -Werror) when debugging is enabledBlue Swirl2009-07-201-10/+10
| | | | | | | I used the following command to enable debugging: perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * */* */*/* Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Update to a hopefully more future proof FSF addressBlue Swirl2009-07-167-14/+7
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-ppc: enable PPC_MFTB for 44xBaojun Wang2009-07-131-6/+6
| | | | | | | | | | | | | | | | | | | According to PPC440 user manual, PPC 440 supports ``mftb'' even it's a preserved instruction: PPC440_UM2013.pdf, p.445, table A-3 when I compile a kernel (2.6.30, bamboo_defconfig/440EP & canyonlands/460EX), I can see ``mftb'' by using ppc-xxx-objdump vmlinux I have also checked the ppc 440x[456], 460S, 464, they also should support mftb. The following patch enable mftb for all ppc 440 variants, including: 440EP, 440GP, 440x4, 440x5 and 460 Signed-off-by: Baojun Wang <wangbj@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* ppc tcg: fix wrong bit/mask of wrteeiBaojun Wang2009-07-131-2/+2
| | | | | Signed-off-by: Baojun Wang <wangbj@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-ppc: fix evmergelo and evmergelohiNathan Froyd2009-07-121-3/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For 32-bit PPC targets, we translated: evmergelo rX, rX, rY as: rX-lo = rY-lo rX-hi = rX-lo which is wrong, because we should be transferring rX-lo first. This problem is fixed by swapping the order in which we write the parts of rX. Similarly, we translated: evmergelohi rX, rX, rY as: rX-lo = rY-hi rX-hi = rX-lo In this case, we can't swap the assignment statements, because that would just cause problems for: evmergelohi rX, rY, rX Instead, we detect the first case and save rX-lo in a temporary variable: tmp = rX-lo rX-lo = rY-hi rX-hi = tmp These problems don't occur on PPC64 targets because we don't split the SPE registers into hi/lo parts for such targets. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-ppc: permit linux-user to read PVRNathan Froyd2009-06-231-1/+7
| | | | | | | | | | Access to the PVR SPR is normally forbidden from userspace apps. The Linux kernel, however, fixes up reads in the appropriate trap handler. To permit applications that read PVR to run on QEMU, then, we need to implement the same handling of PVR reads. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: malc <av1474@comtv.ru>
* Apply TCGV_UNUSED on variables that GCC mistakenly thinks can be usedmalc2009-06-201-0/+6
| | | | uninitialized
* Replace ELF section hack with normal tableBlue Swirl2009-06-172-898/+858
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Concentrate rest of table entries to topBlue Swirl2009-06-171-107/+610
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Concentrate most table entries to topBlue Swirl2009-06-171-422/+291
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Clean up GEN_HANDLER2Blue Swirl2009-06-171-37/+110
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Clean up GEN_HANDLERBlue Swirl2009-06-171-233/+694
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Fix mingw32 build warningsBlue Swirl2009-06-131-1/+15
| | | | | | | | Work around buffer and ioctlsocket argument type signedness problems Suppress a prototype which is unused on mingw32 Expand a macro to avoid warnings from some GCC versions Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* kvm: Add missing bits to support live migrationJan Kiszka2009-05-221-0/+5
| | | | | | | | | | | | This patch adds the missing hooks to allow live migration in KVM mode. It adds proper synchronization before/after saving/restoring the VCPU states (note: PPC is untested), hooks into cpu_physical_memory_set_dirty_tracking() to enable dirty memory logging at KVM level, and synchronizes that drity log into QEMU's view before running ram_live_save(). Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Convert machine registration to use module init functionsAnthony Liguori2009-05-211-11/+0
| | | | | | This cleans up quite a lot of #ifdefs, extern variables, and other ugliness. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Hardware convenience libraryPaul Brook2009-05-191-1/+0
| | | | | | | | | | | | | | The only target dependency for most hardware is sizeof(target_phys_addr_t). Build these files into a convenience library, and use that instead of building for every target. Remove and poison various target specific macros to avoid bogus target dependencies creeping back in. Big/Little endian is not handled because devices should not know or care about this to start with. Signed-off-by: Paul Brook <paul@codesourcery.com>
* target-ppc: expose cpu capability flagsNathan Froyd2009-05-163-138/+140
| | | | | | | | Do this so other pieces of code can make decisions based on the capabilities of the CPU we're emulating. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: malc <av1474@comtv.ru>
* Include assert.h from qemu-common.hPaul Brook2009-05-131-1/+0
| | | | | | | Include assert.h from qemu-common.h and remove other direct uses. cpu-all.h still need to include it because of the dyngen-exec.h hacks Signed-off-by: Paul Brook <paul@codesourcery.com>
* Fix typo that leads to out of bounds array access on big endian systemsmalc2009-05-131-1/+1
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* Fix powerpc 604 reset vectorTristan Gingold2009-04-281-2/+2
| | | | | | | | | According to 604eUM_book (see 8.3.3 Reset inputs p8-54), the IP bit is set for hreset and the vector is at offset 0x100 from the exception prefix. No difference in this area between 604 and 604e. Signed-off-by: Tristan Gingold <gingold@adacore.com>
* Fix PPC resetBlue Swirl2009-04-284-21/+28
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* qemu: introduce qemu_init_vcpu (Marcelo Tosatti)aliguori2009-04-241-2/+1
| | | | | | | | Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
* qemu: per-arch cpu_has_work (Marcelo Tosatti)aliguori2009-04-241-1/+7
| | | | | | | | | | Blue Swirl: fix Sparc32 breakage Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162
* target-ppc: mark a few helpers TCG_CALL_CONST and/or TCG_CALL_PUREaurel322009-04-161-19/+19
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7129 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix ppc-softmmu warnings on OpenBSD hostblueswir12009-04-131-6/+14
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7099 c046a42c-6fe2-441c-8c8c-71466251a162
* Add new command line option -singlestep for tcg single stepping.aurel322009-04-051-4/+1
| | | | | | | | | | | | | | This replaces a compile time option for some targets and adds this feature to targets which did not have a compile time option. Add monitor command to enable or disable single step mode. Modify monitor command "info status" to display single step mode. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
* target-ppc: Explain why the whole TLB is flushed on SR writeaurel322009-03-291-0/+2
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6947 c046a42c-6fe2-441c-8c8c-71466251a162
* target-ppc: avoid nop to override next instructionaurel322009-03-291-3/+3
| | | | | | | | | | | | While searching PC, always store the pc of a new instruction. Instructions that didn't generate tcg code (such as nop) prevented the next one to be referenced. Based on patch for target-alpha, r6930. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6931 c046a42c-6fe2-441c-8c8c-71466251a162
* Make the ELF loader aware of backwards compatibilityblueswir12009-03-131-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most 64 bit architectures I'm aware of support running 32 bit code of the same architecture as well. So x86_64 can run i386 code easily and ppc64 can run ppc code. Unfortunately, the current checks are pretty strict. So you can only load e.g. an x86_64 elf binary on qemu-system-x86_64, but no i386 one. This can get really annoying. I first encountered this issue with my multiboot patch, where qemu-system-x86_64 was unable to load an i386 elf binary because the elf loader rejected it. The same thing happened again on PPC64 now. The firmware we're loading is a PPC32 elf binary, as it's shared with PPC32. But the platform is PPC64. Right now there is a hack for this in the ppc cpu.h definition, that simply sets the type to PPC32 in system emulation mode. While that works fine for the firmware, it's no good if you also want to load a PPC64 kernel with -kernel. So in order to solve this mess, I figured the easiest way is to make the elf loader aware of platforms that are backwards compatible. For now I was only sure that x86_64 does i386 and ppc64 does ppc32, but maybe there are other combinations too. This patch is a prerequisite for having a working -kernel option on PPC64. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6855 c046a42c-6fe2-441c-8c8c-71466251a162
* target-ppc: use the new bswap* TCG opsaurel322009-03-131-114/+15
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6835 c046a42c-6fe2-441c-8c8c-71466251a162
* tcg: rename bswap_i32/i64 functionsaurel322009-03-131-11/+11
| | | | | | | | Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64 Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
* target-ppc: fix commit r6789aurel322009-03-101-2/+2
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6804 c046a42c-6fe2-441c-8c8c-71466251a162
* targe-ppc: optimize mfcr and mtcrfaurel322009-03-093-30/+26
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162
* target-ppc: free a tcg temp variableaurel322009-03-091-0/+1
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6790 c046a42c-6fe2-441c-8c8c-71466251a162
* target-ppc: add support for reading/writing spefscraurel322009-03-091-8/+23
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6789 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix off-by-one errors for Altivec and SPE registersaurel322009-03-071-8/+8
| | | | | | | | | | | | | | | Altivec and SPE both have 34 registers in their register sets, not 35 with a missing register 32. GDB would ask for register 32 of the Altivec (resp. SPE) registers and the code would claim it had zero width. The QEMU GDB stub code would then return an E14 to GDB, which would complain about not being sure whether p packets were supported or not. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6769 c046a42c-6fe2-441c-8c8c-71466251a162
* Disable BAT for 970blueswir12009-03-071-3/+3
| | | | | | | | | | | The 970 doesn't know BAT, so let's not search BATs there. This was only in as a hack for OpenHackWare so it would work on PPC64. Signed-off-by: Alexander Graf <alex@csgraf.de> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6759 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix mfcr on ppc64-softmmuaurel322009-03-071-2/+2
| | | | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6758 c046a42c-6fe2-441c-8c8c-71466251a162
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