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* target-ppc: Remove POWER5+ v0.0 that never existedAlexey Kardashevskiy2015-03-252-5/+2
| | | | | | | | | | | | | | | | IBM uses low 16bits to specify the chip version of a POWER CPU. So there has never been an actual silicon with PVR = 0x003B0000. The first silicon would have PVR 0x003B0100 but it is very unlikely to find it in any machine shipped to any customer as it was too raw. This removes CPU_POWERPC_POWER5P_v00 definition and changes POWER5+ and POWERgs aliases (which are synonyms) to point to POWER5+_v2.1 which can still be found in real machines. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> [agraf: fix commit message] Signed-off-by: Alexander Graf <agraf@suse.de>
* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-64/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | This is improved type checking for the translators -- it's no longer possible to accidentally swap arguments to the branch functions. Note that the code generating backends still manipulate labels as int. With notable exceptions, the scope of the change is just a few lines for each target, so it's not worth building extra machinery to do this change in per-target increments. Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into stagingPeter Maydell2015-03-121-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | misc fixes and cleanups A bunch of fixes all over the place, some of the bugs fixed are actually regressions. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> # gpg: Signature made Wed Mar 11 17:48:30 2015 GMT using RSA key ID D28D5469 # gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" # gpg: aka "Michael S. Tsirkin <mst@redhat.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 0270 606B 6F3C DF3D 0B17 0970 C350 3912 AFBE 8E67 # Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA 8A0D 281F 0DB8 D28D 5469 * remotes/mst/tags/for_upstream: (25 commits) virtio-scsi: remove empty wrapper for cmd virtio-scsi: clean out duplicate cdb field virtio-scsi: fix cdb/sense size uapi/virtio_scsi: allow overriding CDB/SENSE size virtio-scsi: drop duplicate CDB/SENSE SIZE exec: don't include hw/boards for linux-user acpi: specify format for build_append_namestring MAINTAINERS: drop aliguori@amazon.com tpm: Move memory subregion function into realize function virtio-pci: Convert to realize() pci: Convert pci_nic_init() to Error to avoid qdev_init() machine: query mem-merge machine property machine: query dump-guest-core machine property hw/boards: make it safe to include for linux-user machine: query phandle-start machine property machine: query kvm-shadow-mem machine property kvm: add machine state to kvm_arch_init machine: query kernel-irqchip property machine: allowed/required kernel-irqchip support machine: replace qemu opts with iommu property ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * kvm: add machine state to kvm_arch_initMarcel Apfelbaum2015-03-111-1/+1
| | | | | | | | | | | | | | | | | | Needed to query machine's properties. Signed-off-by: Marcel Apfelbaum <marcel@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
* | cpu: Make cpu_init() return QOM CPUState objectEduardo Habkost2015-03-101-8/+1
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of making cpu_init() return CPUArchState, return CPUState. Changes were made using the Coccinelle semantic patch below. @@ typedef CPUState; identifier e; expression args; type CPUArchState; @@ - e = + cpu = cpu_init(args); - if (!e) { + if (!cpu) { ... } - cpu = ENV_GET_CPU(env); + e = cpu->env_ptr; @@ identifier new_env, new_cpu, env, cpu; type CPUArchState; expression args; @@ -{ - CPUState *cpu = ENV_GET_CPU(env); - CPUArchState *new_env = cpu_init(args); - CPUState *new_cpu = ENV_GET_CPU(new_env); +{ + CPUState *cpu = ENV_GET_CPU(env); + CPUState *new_cpu = cpu_init(args); + CPUArchState *new_env = new_cpu->env_ptr; ... } @@ identifier c, cpu_init_func, cpu_model; type StateType, CPUType; @@ -static inline StateType* cpu_init(const char *cpu_model) -{ - CPUType *c = cpu_init_func(cpu_model); ( - if (c == NULL) { - return NULL; - } - return &c->env; | - if (c) { - return &c->env; - } - return NULL; ) -} +#define cpu_init(cpu_model) CPU(cpu_init_func(cpu_model)) @@ identifier cpu_init_func; identifier model; @@ -#define cpu_init(model) (&cpu_init_func(model)->env) +#define cpu_init(model) CPU(cpu_init_func(model)) Signed-off-by: Eduardo Habkost <ehabkost@redhat.com> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Riku Voipio <riku.voipio@iki.fi> Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Max Filippov <jcmvbkbc@gmail.com> [AF: Fixed up cpu_copy() manually] Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Fix warnings from SparseStefan Weil2015-03-091-2/+3
| | | | | | | | | | Sparse report: target-ppc/mmu-hash64.c:353:9: warning: returning void-valued expression target-ppc/mmu-hash64.c:620:9: warning: returning void-valued expression Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add versions to server CPU descriptionsAlexey Kardashevskiy2015-03-092-7/+9
| | | | | | | | | | | | | | | | | | | | 5b79b1c "target-ppc: Create versionless CPU class per family if KVM" added a dynamic CPU class registration with the name of the CPU family which QEMU is running on. For example, this allowed specifying "-cpu POWER7" on every version of POWER7 machine, not just the one which POWER7 was an alias of. I.e. before 5b79b1c, "-cpu POWER7" would not work on real POWER7 2.1 and would work on POWER7 2.3 only. The same story for POWER8. However that patch broke POWER5+ support as POWER5+ CPU uses the same name as the CPU class so dynamic registering of the POWER5+ class failed. This redefines POWER5+ server CPUs by adding a version to them and adding an alias for TCG case. KVM will use dynamically registered CPUs. While we are here, do the same for 970 CPU. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Introduce the Virtual Time Base (VTB) SPR registerCyril Bur2015-03-092-0/+11
| | | | | | | | | | | | | | | | | | | | | This patch adds basic support for the VTB. PowerISA: The Virtual Time Base (VTB) is a 64-bit incrementing counter. Virtual Time Base increments at the same rate as the Time Base until its value becomes 0xFFFF_FFFF_FFFF_FFFF (2 64 - 1); at the next increment its value becomes 0x0000_0000_0000_0000. There is no interrupt or other indication when this occurs. The operation of the Virtual Time Base has the following additional properties. 1. Loading a GPR from the Virtual Time Base has no effect on the accuracy of the Virtual Time Base. 2. Copying the contents of a GPR to the Virtual Time Base replaces the contents of the Virtual Time Base with the contents of the GPR. Signed-off-by: Cyril Bur <cyril.bur@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: force update of msr bits in cpu_post_loadMark Cave-Ayland2015-03-091-1/+7
| | | | | | | | | | | | | Since env->msr has already been restored by the time cpu_post_load is called, make sure that ppc_store_msr() is explicitly called with all msr bits except MSR_TGPR marked as invalid. This solves the issue where MSR flags aren't set correctly when restoring a VM snapshot, in particular the internal env->excp_prefix value when MSR_EP has been altered by a guest. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: move sdr1 value change detection logic to helper_store_sdr1()Mark Cave-Ayland2015-03-092-21/+21
| | | | | | | | | | Otherwise when cpu_post_load calls ppc_store_sdr1() when restoring a VM snapshot the value is deemed unchanged and so the internal env->htab* variables aren't set correctly. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* display cpu id dump stateTristan Gingold2015-03-091-2/+3
| | | | | Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Use right page size with hash table lookupAneesh Kumar K.V2015-03-093-11/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | We look at two sizes specified in ISA (4K, 64K). If not found matching, we consider it 16MB. Without this patch we would fail to lookup address above 16MB range. Below 16MB happened to work before because the kernel have a liner mapping and we always looked up hash for 0xc000000000000000. The actual real address was computed by using the 16MB offset with the real address found with the above hash. Without Fix: (gdb) x/16x 0xc000000001000000 0xc000000001000000 <list_entries+453208>: Cannot access memory at address 0xc000000001000000 (gdb) With Fix: (gdb) x/16x 0xc000000001000000 0xc000000001000000 <list_entries+453208>: 0x00000000 0x00000000 0x00000000 0x00000000 0xc000000001000010 <list_entries+453224>: 0x00000000 0x00000000 0x00000000 0x00000000 0xc000000001000020 <list_entries+453240>: 0x00000000 0x00000000 0x00000000 0x00000000 0xc000000001000030 <list_entries+453256>: 0x00000000 0x00000000 0x00000000 0x00000000 Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-121-6/+3
| | | | | | | | The method by which we count the number of ops emitted is going to change. Abstract that away into some inlines. Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-121-1/+1
| | | | | Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
* exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell2015-01-201-2/+0
| | | | | | | | | | | | | | The TARGET_HAS_ICE #define is intended to indicate whether a target-* guest CPU implementation supports the breakpoint handling. However, all our guest CPUs have that support (the only two which do not define TARGET_HAS_ICE are unicore32 and openrisc, and in both those cases the bp support is present and the lack of the #define is just a bug). So remove the #define entirely: all new guest CPU support should include breakpoint handling as part of the basic implementation. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1420484960-32365-1-git-send-email-peter.maydell@linaro.org
* kvm: extend kvm_irqchip_add_msi_route to work on s390Frank Blaschka2015-01-121-0/+6
| | | | | | | | | | | on s390 MSI-X irqs are presented as thin or adapter interrupts for this we have to reorganize the routing entry to contain valid information for the adapter interrupt code on s390. To minimize impact on existing code we introduce an architecture function to fixup the routing entry. Signed-off-by: Frank Blaschka <frank.blaschka@de.ibm.com> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
* Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' ↵Peter Maydell2015-01-107-110/+323
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Patch queue for ppc - 2015-01-07 New year's release. This time's highlights: - E500: More RAM support - pseries: New SLOF release - Migration fixes - Simplify USB spawning logic, removes support for explicit usb=off - TCG: Simple untansactional TM emulation # gpg: Signature made Wed 07 Jan 2015 15:19:37 GMT using RSA key ID 03FEDC60 # gpg: Good signature from "Alexander Graf <agraf@suse.de>" # gpg: aka "Alexander Graf <alex@csgraf.de>" * remotes/agraf/tags/signed-ppc-for-upstream: (37 commits) hw/ppc/mac_newworld: simplify usb controller creation logic hw/ppc/spapr: simplify usb controller creation logic hw/ppc/mac_newworld: QOMified mac99 machines hw/usb: simplified usb_enabled hw/machine: added machine_usb wrapper hw/ppc: modified the condition for usb controllers to be created for some ppc machines target-ppc: Cast ssize_t to size_t before printing with %zx target-ppc: Mark SR() and gen_sync_exception() as !CONFIG_USER_ONLY PPC: e500: Fix GPIO controller interrupt number target-ppc: Introduce Privileged TM Noops target-ppc: Introduce tcheck target-ppc: Introduce TM Noops target-ppc: Introduce tbegin target-ppc: Introduce TEXASRU Bit Fields target-ppc: Power8 Supports Transactional Memory target-ppc: Introduce tm_enabled Bit to CPU State target-ppc: Introduce Feature Flag for Transactional Memory target-ppc: Introduce Instruction Type for Transactional Memory pseries: Update SLOF firmware image to 20141202 PPC: Fix crash on spapr_tce_table_finalize() ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-ppc: Mark SR() and gen_sync_exception() as !CONFIG_USER_ONLYPeter Maydell2015-01-071-0/+5
| | | | | | | | | | | | | | | | | | The functions SR() and gen_sync_exception() are only used in softmmu configs; wrap them in #ifndef CONFIG_USER_ONLY to suppress clang warnings on the linux-user builds. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Introduce Privileged TM NoopsTom Musta2015-01-071-0/+38
| | | | | | | | | | | | | | | | | | | | Add the supervisory Transactional Memory instructions treclaim. and trechkpt. The implementation is a degenerate one that simply checks privileged state, TM availability and then sets CR[0] to 0b0000, just like the unprivileged noops. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Introduce tcheckTom Musta2015-01-071-0/+17
| | | | | | | | | | | | | | | | | | | | Add a degenerate implementation of the Transaction Check (tcheck) instruction. Since transaction always immediately fail, this implementation simply sets CR[BF] to 0b1000, i.e. TDOOMED = 1 and MSR[TS] == 0. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Introduce TM NoopsTom Musta2015-01-071-0/+38
| | | | | | | | | | | | | | | | | | | | | | Add degenerate implementations of the non-privileged Transactional Memory instructions tend., tabort*. and tsr. This implementation simply checks the MSR[TM] bit and then sets CR0 to 0b0000. This is a reasonable degenerate implementation since transactions are never allowed to begin and hence MSR[TS] is always 0b00. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Introduce tbeginTom Musta2015-01-073-0/+36
| | | | | | | | | | | | | | | | | | Provide a degenerate implementation of the tbegin instruction. This implementation always fails the transaction, recording the failure per Book II Section 5.3.2 of the Power ISA V2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Introduce TEXASRU Bit FieldsTom Musta2015-01-071-0/+20
| | | | | | | | | | | | | | Define mnemonics for the various bit fields in the Transaction EXception And Summary Register (TEXASR). Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Power8 Supports Transactional MemoryTom Musta2015-01-071-2/+3
| | | | | | | | | | | | | | | | | | The Power8 processor implements the Transactional Memory Facility as defined in Power ISA 2.07. Update the initialization code to indicate this. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Introduce tm_enabled Bit to CPU StateTom Musta2015-01-071-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Add a bit (tm_enabled) to CPU state that mirrors the MSR[TM] bit. This is analogous to the other "available" bits in the MSR (FP, VSX, etc.). NOTE: Since MSR[TM] occupies big-endian bit 31, the code is wrapped with a PPC64 bit check. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Introduce Feature Flag for Transactional MemoryTom Musta2015-01-071-0/+2
| | | | | | | | | | | | | | | | Add a flag (POWERPC_FLAG_TM) for the Transactional Memory Facility introduced in Power ISA 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Introduce Instruction Type for Transactional MemoryTom Musta2015-01-071-1/+3
| | | | | | | | | | | | | | | | Add a category (PPC2_TM) for the Transactional Memory instructions introduced in Power ISA 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: explicitly save page table headers in big endianCédric Le Goater2015-01-071-3/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when the page tables are saved, the kvm_get_htab_header structs and the ptes are assumed being big endian and dumped as a indistinct blob in the statefile. This is no longer true when the host is little endian and this breaks restoration. This patch unfolds the kvmppc_save_htab routine to write explicitly the kvm_get_htab_header structs in big endian. The ptes are left untouched. Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Eliminate set_fprf Argument From helper_compute_fprfTom Musta2015-01-073-38/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The set_fprf argument to the helper_compute_fprf helper function is no longer necessary -- the helper is only invoked when FPSCR[FPRF] is going to be set. Eliminate the unnecessary argument from the function signature and its corresponding implementation. Change the return value of the helper to "void". Update the name of the local variable "ret" to "fprf", which now makes more sense. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Eliminate set_fprf Argument From gen_compute_fprfTom Musta2015-01-071-15/+23
| | | | | | | | | | | | | | | | | | The set_fprf argument to the gen_compute_fprf() utility is no longer needed -- gen_compute_fprf() is now called only when FPRF is actually computed and set. Eliminate the obsolete argument. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Fully Migrate to gen_set_cr1_from_fpscrTom Musta2015-01-071-22/+33
| | | | | | | | | | | | | | | | | | Eliminate the set_rc argument from the gen_compute_fprf utility and the corresponding (and incorrect) implementation. Replace it with calls to the gen_set_cr1_from_fpscr() utility. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: mffs. Should Set CR1 from FPSCR BitsTom Musta2015-01-071-1/+3
| | | | | | | | | | | | | | | | Update the Move From FPSCR (mffs.) instruction to correctly set CR[1] from FPSCR[FX,FEX,VX,OX]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Fix Floating Point Move Instructions That Set CR1Tom Musta2015-01-071-20/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | The Floating Point Move instructions (fmr., fabs., fnabs., fneg., and fcpsgn.) incorrectly copy FPSCR[FPCC] instead of [FX,FEX,VX,OX]. Furthermore, the current code does this via a call to gen_compute_fprf, which is awkward since these instructions do not actually set FPRF. Change the code to use the gen_set_cr1_from_fpscr utility. Signed-off-by: Tom Musta <tommusta@gmail.com> [agraf: whitespace fixes] Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: VXSQRT Should Not Be Set for NaNsTom Musta2015-01-071-12/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Power ISA square root instructions (fsqrt[s], frsqrte[s]) must set the FPSCR[VXSQRT] flag when operating on a negative value. However, NaNs have no sign and therefore this flag should not be set when operating on one. Change the order of the checks in the helper code. Move the SNaN-to-QNaN macro to the top of the file so that it can be re-used. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Load/Store Vector Element Storage AlignmentTom Musta2015-01-071-8/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Load Vector Element Indexed and Store Vector Element Indexed instructions compute an effective address in the usual manner. However, they truncate that address to the natural boundary. For example, the lvewx instruction will ignore the least significant two bits of the address and thus load the aligned word of storage. Fix the generators for these instruction to properly perform this truncation. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* | gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
| | | | | | | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | translate: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-12/+12
| | | | | | | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | target-ppc: pass DisasContext to SPR generator functionsPaolo Bonzini2014-12-233-137/+133
|/ | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@ispras.ru> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* qemu-log: add log category for MMU infoAntony Pavlov2014-12-163-29/+33
| | | | | | | | | | | | | | | | | | | | | | | Running barebox on qemu-system-mips* with '-d unimp' overloads stderr by very very many mips_cpu_handle_mmu_fault() messages: mips_cpu_handle_mmu_fault address=b80003fd ret 0 physical 00000000180003fd prot 3 mips_cpu_handle_mmu_fault address=a0800884 ret 0 physical 0000000000800884 prot 3 mips_cpu_handle_mmu_fault pc a080cd80 ad b80003fd rw 0 mmu_idx 0 So it's very difficult to find LOG_UNIMP message. The mips_cpu_handle_mmu_fault() messages appear on enabling ANY logging! It's not very handy. Adding separate log category for *_cpu_handle_mmu_fault() logging fixes the problem. Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Acked-by: Alexander Graf <agraf@suse.de> Reviewed-by: Richard Henderson <rth@twiddle.net> Message-id: 1418489298-1184-1-git-send-email-antonynpavlov@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-ppc: Altivec's mtvscr Decodes Wrong RegisterTom Musta2014-11-201-1/+1
| | | | | | | | | | The Move to Vector Status and Control Register (mtvscr) instruction uses VRB as the source register. Fix the code generator to correctly decode the VRB field. That is, use "rB(ctx->opcode)" instead of "rD(ctx->opcode)". Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Fix breakpoint registers for e300Fabien Chouteau2014-11-201-26/+26
| | | | | | | | In the previous patch, the registers were added to init_proc_G2LE instead of init_proc_e300. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Fix Altivec Round OpcodesTom Musta2014-11-041-6/+6
| | | | | | | | Correct the opcodes for the vrfim, vrfin and vrfiz instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Fix vcmpbfp. Unordered CaseTom Musta2014-11-041-1/+1
| | | | | | | | | Fix the implementation of Vector Compare Bounds Single Precision. Specifically, fix the case where the operands are unordered -- since the result is non-zero, the CR[6] field should be set to zero. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Fix Altivec ShiftsTom Musta2014-11-041-11/+2
| | | | | | | | | Fix the implementation of the Altivec shift left and shift right instructions (vsl, vsr) which erroneously inverts shift direction on big endian hosts. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: simplify AES emulationAurelien Jarno2014-11-041-2/+2
| | | | | | | | | | | | | This patch simplifies the AES code, by directly accessing the newly added S-Box, InvS-Box tables instead of recreating them by using the AES_Te and AES_Td tables. Cc: Alexander Graf <agraf@suse.de> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: do not look at the MMU index to detect PR/HV modePaolo Bonzini2014-11-041-88/+77
| | | | | | | | | The MMU index is an internal detail that should not be needed by the translator (except to generate loads and stores). Look at the MSR directly. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: kvm: Fix memory overflow issue about strncat()Chen Gang2014-11-041-4/+4
| | | | | | | | | | | | strncat() will append additional '\0' to destination buffer, so need additional 1 byte for it, or may cause memory overflow, just like other area within QEMU have done. And can use g_strdup_printf() instead of strncat(), which may be more easier understanding. Signed-off-by: Chen Gang <gang.chen.5i5j@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Fix an invalid free in opcode table handling code.Bharata B Rao2014-11-041-3/+16
| | | | | | | | | Opcode table has direct, indirect and double indirect handlers, but ppc_cpu_unrealizefn() frees direct handlers which are never allocated and never frees double indirect handlers. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Use macros in opcodes table handling codeBharata B Rao2014-11-042-11/+16
| | | | | | | | | | Define and use macros instead of direct numbers wherever possible in ppc opcodes table handling code. This doesn't change any code functionality. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc : Add new processor type 440x5wDFPUPierre Mallard2014-11-042-0/+41
| | | | | | | | This patch add a new processor type 440x5wDFPU for Virtex 5 PPC440 with an external APU FPU in double precision mode Signed-off-by: Pierre Mallard <mallard.pierre@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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