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* target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64Pierre Mallard2014-11-045-22/+16
| | | | | | | | This patch remove limitation for fc[tf]id[*] on 32 bits targets and add a new insn flag for signed integer 64 conversion PPC2_FP_CVT_S64 Signed-off-by: Pierre Mallard <mallard.pierre@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Implement IVOR[59] By Default for Book ETom Musta2014-11-041-1/+1
| | | | | | | | | Adjust the IVOR mask for generic Book E implementation to support bit 59. This is consistent with the Power ISA. Signed-off-by: Tom Musta <tommusta@gmail.com> Reported-by: Pierre Mallard <mallard.pierre@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Fix kvmppc_set_compat to use negotiated cpu-versionAlexey Kardashevskiy2014-11-041-1/+1
| | | | | | | | | | | By mistake, QEMU uses the maximum compatibility level from the command line instead of the value negotiated in client-architecture-support call. This replaces @max_compat with @cpu_version. This only affects guests which do not support the host CPU. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: compute mask from BI using right shiftPaolo Bonzini2014-11-041-3/+3
| | | | | | | | | | This will match the code we use in fpu_helper.c when we flip CRF_* bit-endianness. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: rename gen_set_cr6_from_fpscrPaolo Bonzini2014-11-041-7/+7
| | | | | | | | | It sets CR1, not CR6 (and the spec agrees). Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: fix result of DLMZB when no zero bytes are foundPaolo Bonzini2014-11-041-0/+1
| | | | | | | | | It must return 8 and place 8 in XER, but the current code uses i directly which is 9 at this point of the code. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: use CRF_* in int_helper.cPaolo Bonzini2014-11-041-6/+6
| | | | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* qdev: Drop legacy_name from qdev propertiesGonglei2014-10-151-1/+0
| | | | | | | | | | | The legacy_name is useless now, better help information is provided by description field of property. Cc: Markus Armbruster <armbru@redhat.com> Signed-off-by: Gonglei <arei.gonglei@huawei.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* qdev: Add description field in PropertyInfo structGonglei2014-10-151-0/+1
| | | | | | | | | | | | The descriptions can serve as documentation in the code, and they can be used to provide better help. Cc: Markus Armbruster <armbru@redhat.com> Signed-off-by: Gonglei <arei.gonglei@huawei.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Use cpu_exec_interrupt qom hookRichard Henderson2014-09-254-3/+19
| | | | | | | Cc: qemu-ppc@nongnu.org Signed-off-by: Richard Henderson <rth@twiddle.net> Message-id: 1410626734-3804-22-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-ppc: Use cpu_exec_enter qom hookRichard Henderson2014-09-251-0/+9
| | | | | | | | Cc: qemu-ppc@nongnu.org Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Message-id: 1410626734-3804-6-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-ppc: Implement mulldo with TCGTom Musta2014-09-083-30/+14
| | | | | | | | | | Optimize mulldo by using the muls2_i64 operation rather than a helper. Eliminate the obsolete helper code. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Clean up mullwoTom Musta2014-09-081-8/+3
| | | | | | | | | | | | Simplify the implementation of mullwo. For 64 bit CPUs, the result is the concatenation of the upper and lower parts of the muls2_i32 operation, which may be slightly better than deposit. For 32 bit CPUs, the lower part of the muls_i32 operation is moved into the target GPR. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Clean Up mullwTom Musta2014-09-081-3/+2
| | | | | | | | | | Eliminate the unecessary ext32s TCG operation and make the multiplication operation explicitly 32 bit. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Optimize rlwnm MB=0 ME=31Tom Musta2014-09-081-22/+34
| | | | | | | | | | Optimize the special case of rlwnm where MB=0 and ME=31. This can be implemented using a ROTL. Suggested-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Optimize rlwinm MB=0 ME=31Tom Musta2014-09-081-0/+6
| | | | | | | | | | Optimize the special case of rlwinm where MB=0 and ME=31. This can be implemented as a 32-bit ROTL. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Special Case of rlwimi Should Use DepositTom Musta2014-09-081-6/+3
| | | | | | | | | | | The special case of rlwimi where MB <= ME and SH = 31-ME can be implemented with a single TCG deposit operation. This replaces the less general case of SH = MB = 0 and ME = 31. Signed-off-by: Tom Musta <tommusta@gmail.com> Suggested-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: KVM: Use vm check_extension for pv hcallAlexander Graf2014-09-081-1/+1
| | | | | | | | | | | To find out whether we support the KVM hypercall interface we need to ask KVM on the VM level rather than the global KVM level, because Book3S HV KVM does not support it and we play conservative when both HV and PR are loaded. So instead, use the VM helper that falls back to global KVM enumeration. That should cover all cases. Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Bug Fix: sradTom Musta2014-09-081-1/+1
| | | | | | | | | | | | | | | | | Fix the check for carry in the srad helper to properly construct the mask -- a "1ULL" must be used (instead of "1") in order to get the desired result. Example: R3 8000000000000000 R4 F3511AD4A2CD4C38 srad 3,3,4 Should *not* set XER[CA] but does without this patch. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Bug Fix: srawiTom Musta2014-09-081-1/+1
| | | | | | | | | | | | | | | | For 64 bit implementations, the special case of a shift by zero should result in the sign extension of the least significant 32 bits of the source GPR (not a direct copy of the 64 bit source GPR). Example: R3 A6212433228F41DC srawi 3,3,0 R3 expected : 00000000228F41DC R3 actual : A6212433228F41DC (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Bug Fix: mulldo OV DetectionTom Musta2014-09-081-2/+12
| | | | | | | | | | | | | | | | | Fix the code to properly detect overflow; the 128 bit signed product must have all zeroes or all ones in the first 65 bits otherwise OV should be set. Example: R3 45F086A5D5887509 R4 0000000000000002 mulldo 3,3,4 Should set XER[OV]. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Bug Fix: mullwTom Musta2014-09-081-0/+11
| | | | | | | | | | | | | | | | | | | For 64-bit implementations, the mullw result is the 64 bit product of the sign-extended least significant 32 bits of the source registers. Fix the code to properly sign extend the source operands and produce a 64 bit product. Example: R3 00000000002F37A0 R4 41C33D242F816715 mullw 3,3,4 R3 expected : 0008C3146AE0F020 R3 actual : 000000006AE0F020 (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Bug Fix: mullwoTom Musta2014-09-081-0/+9
| | | | | | | | | | | | | | | | | On 64-bit implementations, the mullwo result is the 64 bit product of the signed 32 bit operands. Fix the implementation to properly deposit the upper 32 bits into the target register. Example: R3 0407DED115077586 R4 53778DF3CA992E09 mullwo 3,3,4 R3 expected : FB9D02730D7735B6 R3 actual : 000000000D7735B6 (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Bug Fix: rlwimiTom Musta2014-09-081-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The rlwimi specification includes the ROTL32 operation, which is defined to be a left rotation of two copies of the least significant 32 bits of the source GPR. The current implementation is incorrect on 64-bit implementations in that it rotates a single copy of the least significant 32 bits, padding with zeroes in the most significant bits. Fix the code to properly implement this ROTL32 operation. Also fix the special case of MB=31 and ME=0 to copy the entire contents of the source GPR. Examples: R3 FFFFFFFFFFFFFFF0 rlwimi 3,3,29,14,1 R3 expected : 1FFFFFFE3FFFFFFE R3 actual : 000000003FFFFFFE (without this patch) R3 ED7EB4DD824F0853 rlwimi 3,3,10,31,0 R3 expected : 3C214E09024F0853 R3 actual : 00000000024F0853 (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Bug Fix: rlwnmTom Musta2014-09-081-9/+9
| | | | | | | | | | | | | | | | | | | | | | | The rlwnm specification includes the ROTL32 operation, which is defined to be a left rotation of two copies of the least significant 32 bits of the source GPR. The current implementation is incorrect on 64-bit implementations in that it rotates a single copy of the least significant 32 bits, padding with zeroes in the most significant bits. Fix the code to properly implement this ROTL32 operation. Example: R3 = 0000000000000002 R4 = 7FFFFFFFFFFFFFFF rlwnm 3,3,4,31,16 R3 expected : 0000000100000001 R3 actual : 0000000000000001 (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Bug Fix: rlwinmTom Musta2014-09-081-5/+3
| | | | | | | | | | | | | | | | | | | | | | The rlwinm specification includes the ROTL32 operation, which is defined to be a left rotation of two copies of the least significant 32 bits of the source GPR. The current implementation is incorrect on 64-bit implementations in that it rotates a single copy of the least significant 32 bits, padding with zeroes in the most significant bits. Fix the code to properly implement this ROTL32 operation. Example: R3 = F7487D82EC6F75DF rlwinm 3,3,5,12,4 R3 expected : 8DEEBBFD880EBBFD R3 actual : 00000000880EBBFD (without this fix) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Add hw breakpoint watchpoint supportBharat Bhushan2014-09-081-15/+219
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds hardware breakpoint and hardware watchpoint support for ppc. On BOOKE architecture we cannot share debug resources between QEMU and guest because: When QEMU is using debug resources then debug exception must be always enabled. To achieve this we set MSR_DE and also set MSRP_DEP so guest cannot change MSR_DE. When emulating debug resource for guest we want guest to control MSR_DE (enable/disable debug interrupt on need). So above mentioned two configuration cannot be supported at the same time. So the result is that we cannot share debug resources between QEMU and Guest on BOOKE architecture. In the current design QEMU gets priority over guest, this means that if QEMU is using debug resources then guest cannot use them and if guest is using debug resource then qemu can overwrite them. When QEMU is not able to handle debug exception then we inject program exception to guest. Yes program exception NOT debug exception and the reason is: 1) QEMU and guest not sharing debug resources 2) For software breakpoint QEMU uses a ehpriv-1 instruction; So there cannot be any reason that we are in qemu with exit reason KVM_EXIT_DEBUG for guest set debug exception, only possibility is guest executed ehpriv-1 privilege instruction and that's why we are injecting program exception. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Add software breakpoint supportBharat Bhushan2014-09-081-14/+79
| | | | | | | | | | | | | | | | This patch allow insert/remove software breakpoint. When QEMU is not able to handle debug exception then we inject program exception to guest because for software breakpoint QEMU uses a ehpriv-1 instruction; So there cannot be any reason that we are in qemu with exit reason KVM_EXIT_DEBUG for guest set debug exception, only possibility is guest executed ehpriv-1 privilege instruction and that's why we are injecting program exception. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> [agraf: make deflect comment booke/book3s agnostic] Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: synchronize excp_vectors for injecting exceptionBharat Bhushan2014-09-081-0/+27
| | | | | | | | | This patch synchronizes env->excp_vectors[] with env->iovr[]. This is required for using the existing interrupt injection mechanism for kvm. Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: debug stub: Get trap instruction opcode from KVMBharat Bhushan2014-09-081-0/+4
| | | | | | | | Get trap instruction opcode from KVM and this opcode will be used for setting software breakpoint in following patch Signed-off-by: Bharat Bhushan <Bharat.Bhushan@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* spapr: add uuid/host details to device treeNikunj A Dadhania2014-09-082-1/+24
| | | | | | | | | | | | | Useful for identifying the guest/host uniquely within the guest. Adding following properties to the guest root node. vm,uuid - uuid of the guest host-model - Host model number host-serial - Host machine serial number hypervisor type - Tells its "kvm" Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* spapr: Add support for new NMI interfaceAlexey Kardashevskiy2014-08-252-0/+9
| | | | | | | | | | | | This implements an NMI interface POWERPC SPAPR machine. This enables an "nmi" HMP/QMP command supported on SPAPR. This calls POWERPC_EXCP_RESET (vector 0x100) in the guest to deliver NMI to every CPU. The expected result is XMON (in-kernel debugger) invocation. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova2014-08-121-0/+3
| | | | | Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* spapr: Move RMA memory region registration codeAlexey Kardashevskiy2014-07-152-12/+5
| | | | | | | | | | | | | | | | | | | | | | PPC970 does not support VRMA (virtual RMA) so real memory required for SLOF to execute must be allocated by the KVM_ALLOCATE_RMA ioctl. Later this memory is used as a part of the guest RAM area. The RMA allocating code also registers a memory region for this piece of RAM. We are going to simplify memory regions layout: RMA memory region will be a subregion in the RAM memory region, both starting from zero. This way we will not have to take care of start address alignment for the piece of RAM next to the RMA. This moves memory region business closer to the RAM memory region creation/allocation code. As this is a mechanical patch, no change in behaviour is expected. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> [agraf: fix compilation on non-kvm systems] Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Fix number of threads per core limitAlexey Kardashevskiy2014-07-151-13/+5
| | | | | | | | | | | | | | | | | | | | | | The number of threads per core is different for POWER6/7/8 CPUs. Guest systems do not expect to see more threads per core than a specific CPU supports so we need to limit this number. This limit is implemented by ppc_get_compat_smt_threads(). However it has a problem as it checks for PCR (Processor Compatibility Register) mask, 2.05 means 2 threads per core, 2.06 - 4 threads. For POWER8 one would expect PCR_COMPAT_2_07 bit set and ppc_get_compat_smt_threads() checking for it to return 8 threads per core. But the latest PowerISA spec now is 2.07 and there is no 2.07 compatibility mode defined, QEMU does not define it either (will be in PowerISA 2.08). Instead of relying on a PCR mask, this uses kvmppc_smt_threads() which returns the maximum supported threads number for KVM or 1 for TCG. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Remove POWER7+ and POWER8E familiesAlexey Kardashevskiy2014-07-082-73/+4
| | | | | | | | | | | | | | | | POWER8E is architecturally equal to POWER8 and POWER7+ is equal to POWER7. Also no user space tool makes any difference for CPU node name in the device tree (such as PowerPC,POWER7@0 vs. PowerPC,POWER7+@0). So there is no point in emulating POWER7+ and POWER8E apart from POWER7 and POWER8. Also, the previos patch implemented multiple PVR mask support per CPU class so POWER7 class now covers both POWER7 and POWER7+ CPUs, same is valid for POWER8/8E. This removes POWER7+ and POWER8E classes. This replaces references to POWER7P/POWER8E families with POWER7/POWER8 families. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add pvr_match() callbackAlexey Kardashevskiy2014-07-084-21/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far it was enough to have a base PVR value and mask per CPU family such as POWER7 or POWER8. However there CPUs which are completely architecturally compatible but have different PVRs such as POWER7/POWER7+ and POWER8/POWER8E. For these CPUs, top 16 bits are CPU family and low 16 bits are the version. The families have PVR base values different enough so defining a mask which would cover both (or potentially more) CPUs within the family is not possible. This adds a pvr_match() callback to PowerPCCPUClass. The default handler simply compares PVR defined in the class. This implements ppc_pvr_match_power7/ppc_pvr_match_power8 callbacks for POWER7/8 families. These check for POWER7/POWER7+ and POWER8/POWER8E. This changes ppc_cpu_compare_class_pvr_mask() not to check masks but use the pvr_match() callback. Since all server CPUs use the same mask, this defines one mask value - CPU_POWERPC_POWER_SERVER_MASK - which is used everywhere now. This removes other mask definitions. This removes pvr_mask from PowerPCCPUClass as it is not used anymore. This removes pvr initialization for POWER7/8 families as it is not used to find the class, the pvr_match() callback is used instead. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Fix booke206 TLB with phys addrs > 32bitAlexander Graf2014-07-081-3/+3
| | | | | | | | We were truncating physical addresses to 32bit when using qemu-system-ppc with a booke206 TLB implementation. This patch fixes that and makes the full address space available. Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Fix gdbstub for ppc64le-linux-userRichard Henderson2014-07-081-19/+15
| | | | | | | | | The bswap that's needed for system mode isn't required for user mode, and in fact breaks debugging. Signed-off-by: Richard Henderson <rth@twiddle.net> [agraf: fix apple gdbstub implementation] Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Change default cpu for ppc64le-linux-userRichard Henderson2014-07-081-0/+4
| | | | | | | | | | The default, 970fx, doesn't support MSR_LE. So even though we set LE in ppc_cpu_reset, it gets cleared again in hreg_store_msr. Error out if a user-selected cpu model doesn't support LE. Signed-off-by: Richard Henderson <rth@twiddle.net> [agraf: switch to POWER7 as default for BE and LE] Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: enable virtio endian ambivalent supportGreg Kurz2014-06-292-0/+17
| | | | | | | | | The device endianness is the cpu endianness at device reset time. Signed-off-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
* target-ppc: Add support for POWER8 pvr 0x4D0000Alexey Kardashevskiy2014-06-273-6/+24
| | | | | | | | | | | | | | | | | | | | | | | | At the moment QEMU knows about one version of POWER8 CPU with PVR 0x4B.0000. This CPU class is defined as "POWER8". The linux kernel names it as "POWER8E" which is different from the name QEMU uses. Now we get another version of POWER8 which is architecturally equivalent to POWER8E but has different PVR 0x4D.0000 so QEMU fails to find a PPC CPU class on these machines. The linux kernel names these CPUs as "POWER8". This renames the existing "POWER8" to "POWER8E" to be more precise and stay in sync with the linux kernel. This adds a new "POWER8" family which calls POWER8E class init function and defines own PVR mask (used to match a CPU class) and desc (used to create dynamic version-less CPU class). This does not change CPU class fw_name attribute as the host POWER8 firmware keeps using "PowerPC,POWER8" on both POWER8 and POWER8E. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Remove unused gen_qemu_ld8s()Peter Maydell2014-06-271-5/+0
| | | | | | | The gen_qemu_ld8s() function is unused; remove it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Remove unused IMM and d extract helpersPeter Maydell2014-06-271-3/+0
| | | | | | | | | Remove the definition of the IMM and d extract helpers; these seem to have been added as part of the initial PPC support in 2003 but never actually used. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Alexander Graf <agraf@suse.de>
* spapr_iommu: Make in-kernel TCE table optionalAlexey Kardashevskiy2014-06-272-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | POWER KVM supports an KVM_CAP_SPAPR_TCE capability which allows allocating TCE tables in the host kernel memory and handle H_PUT_TCE requests targeted to specific LIOBN (logical bus number) right in the host without switching to QEMU. At the moment this is used for emulated devices only and the handler only puts TCE to the table. If the in-kernel H_PUT_TCE handler finds a LIOBN and corresponding table, it will put a TCE to the table and complete hypercall execution. The user space will not be notified. Upcoming VFIO support is going to use the same sPAPRTCETable device class so KVM_CAP_SPAPR_TCE is going to be used as well. That means that TCE tables for VFIO are going to be allocated in the host as well. However VFIO operates with real IOMMU tables and simple copying of a TCE to the real hardware TCE table will not work as guest physical to host physical address translation is requited. So until the host kernel gets VFIO support for H_PUT_TCE, we better not to register VFIO's TCE in the host. This adds a place holder for KVM_CAP_SPAPR_TCE_VFIO capability. It is not in upstream yet and being discussed so now it is always false which means that in-kernel VFIO acceleration is not supported. This adds a bool @vfio_accel flag to the sPAPRTCETable device telling that sPAPRTCETable should not try allocating TCE table in the host kernel for VFIO. The flag is false now as at the moment there is no VFIO. This adds an vfio_accel parameter to spapr_tce_new_table(), the semantic is the same. Since there is only emulated PCI and VIO now, the flag is set to false. Upcoming VFIO support will set it to true. This is a preparation patch so no change in behaviour is expected Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Add support for Apple gdb in gdbstubAlexander Graf2014-06-273-0/+147
| | | | | | | | | | | | The Apple gdbstub protocol is different from the normal gdbstub protocol used on PowerPC. Add support for the different variant, so that we can use Apple's gdb to debug guest code. Keep in mind that the switch is a compile time option. We can't detect during runtime whether a gdb connecting to us is an upstream gdb or an Apple gdb. Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: fixed translation of mcrxr instructionSorav Bansal2014-06-271-2/+3
| | | | | | | | | | | | | | | Fixed bug in gen_mcrxr() in target-ppc/translate.c: The XER[SO], XER[OV], and XER[CA] flags are stored in the least significant bit (bit 0) of their respective registers. They need to be shifted left (by their respective offsets) to generate the final XER value. The old translation code for the 'mcrxr' instruction was assuming that the flags are stored in bit 2, and was shifting them right (incorrectly) Signed-off-by: Sorav Bansal <sbansal@cse.iitd.ernet.in> Reviewed-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add DFP to Emulated Instructions FlagTom Musta2014-06-271-1/+1
| | | | | | | | | | Decimal Floating Point is emulated, so add it the mask. This will fix the erroneous message: Warning: Disabling some instructions which are not emulated by TCG (0x0, 0x4) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Fix compiler warningStefan Weil2014-06-241-2/+1
| | | | | | | | | | | | | | | | | | gcc reports a warning which is usually wrong: target-ppc/dfp_helper.c: In function ‘dfp_get_digit’: target-ppc/dfp_helper.c:417:1: warning: control reaches end of non-void function [-Wreturn-type] The compiler shows the warning if assert is not marked with the noreturn attribute or if the code is compiled with -DNDEBUG. Using g_assert_not_reached better documents the intention and does not have these problems. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* PPC: KVM: Make pv hcall endian agnosticAlexander Graf2014-06-161-8/+8
| | | | | | | | | | | | | | | | There were a few revisions of the Linux kernel that incorrectly swapped the hcall instructions when they saw ePAPR compliant hypercalls. We already have fixups for those in place when running with PR KVM, but HV KVM and systems that don't implement hypercalls at all are still broken because they fall back to the QEMU implementation of fallback hypercalls. So let's make the fallback hypercall instruction path endian agnostic. This only really works well for 64bit guests, but I don't think there are any 32bit systems left that don't implement real pv hcall support, so we'll never get into this code path. Signed-off-by: Alexander Graf <agraf@suse.de>
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