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* ppc: Generalize the kvmppc_get_clockfreq() functionDavid Gibson2011-10-301-11/+24
| | | | | | | | | | | | | | | Currently the kvmppc_get_clockfreq() function reads the host's clock frequency from /proc/device-tree, which is useful to past to the guest in KVM setups. However, there are some other host properties advertised in the device tree which can also be relevant to the guests. This patch, therefore, replaces kvmppc_get_clockfreq() which can retrieve any named, single integer property from the host device tree's CPU node. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* Set an invalid-bits mask for each SPE instructionsFabien Chouteau2011-10-301-229/+271
| | | | | | | | | | | SPE instructions are defined by pairs. Currently, the invalid-bits mask is set for the first instruction, but the second one can have a different mask. example: GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* pseries: Use Book3S-HV TCE acceleration capabilitiesDavid Gibson2011-10-302-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | The pseries machine of qemu implements the TCE mechanism used as a virtual IOMMU for the PAPR defined virtual IO devices. Because the PAPR spec only defines a small DMA address space, the guest VIO drivers need to update TCE mappings very frequently - the virtual network device is particularly bad. This means many slow exits to qemu to emulate the H_PUT_TCE hypercall. Sufficiently recent kernels allow this to be mitigated by implementing H_PUT_TCE in the host kernel. To make use of this, however, qemu needs to initialize the necessary TCE tables, and map them into itself so that the VIO device implementations can retrieve the mappings when they access guest memory (which is treated as a virtual DMA operation). This patch adds the necessary calls to use the KVM TCE acceleration. If the kernel does not support acceleration, or there is some other error creating the accelerated TCE table, then it will still fall back to full userspace TCE implementation. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* pseries: Allow KVM Book3S-HV on PPC970 CPUSDavid Gibson2011-10-302-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | At present, using the hypervisor aware Book3S-HV KVM will only work with qemu on POWER7 CPUs. PPC970 CPUs also have hypervisor capability, but they lack the VRMA feature which makes assigning guest memory easier. In order to allow KVM Book3S-HV on PPC970, we need to specially allocate the first chunk of guest memory (the "Real Mode Area" or RMA), so that it is physically contiguous. Sufficiently recent host kernels allow such contiguous RMAs to be allocated, with a kvm capability advertising whether the feature is available and/or necessary on this hardware. This patch enables qemu to use this support, thus allowing kvm acceleration of pseries qemu machines on PPC970 hardware. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de> --- agraf: fix to use memory api
* pseries: Support SMT systems for KVM Book3S-HVDavid Gibson2011-10-303-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | Alex Graf has already made qemu support KVM for the pseries machine when using the Book3S-PR KVM variant (which runs the guest in usermode, emulating supervisor operations). This code allows gets us very close to also working with KVM Book3S-HV (using the hypervisor capabilities of recent POWER CPUs). This patch moves us another step towards Book3S-HV support by correctly handling SMT (multithreaded) POWER CPUs. There are two parts to this: * Querying KVM to check SMT capability, and if present, adjusting the cpu numbers that qemu assigns to cause KVM to assign guest threads to cores in the right way (this isn't automatic, because the POWER HV support has a limitation that different threads on a single core cannot be in different guests at the same time). * Correctly informing the guest OS of the SMT thread to core mappings via the device tree. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: booke timersFabien Chouteau2011-10-062-0/+66
| | | | | | | | | | While working on the emulation of the freescale p2010 (e500v2) I realized that there's no implementation of booke's timers features. Currently mpc8544 uses ppc_emb (ppc_emb_timers_init) which is close but not exactly like booke (for example booke uses different SPR). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* KVM: PPC: Use HIOR setting for -M pseries with PR KVMAlexander Graf2011-10-061-3/+22
| | | | | | | | | | | | When running with PR KVM, we need to set HIOR directly. Thankfully there is now a new interface to set registers individually so we can just use that and poke HIOR into the guest vcpu's HIOR register. While at it, this also sets SDR1 because -M pseries requires it to run. With this patch, -M pseries works properly with PR KVM. Signed-off-by: Alexander Graf <agraf@suse.de>
* Gdbstub: handle read of fpscrFabien Chouteau2011-10-061-2/+1
| | | | | Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* Implement POWER7's CFAR in TCGDavid Gibson2011-10-063-1/+58
| | | | | | | | | | | | | | | This patch implements support for the CFAR SPR on POWER7 (Come From Address Register), which snapshots the PC value at the time of a branch or an rfid. The latest powerpc-next kernel also catches it and can show it in xmon or in the signal frames. This works well enough to let recent kernels boot (which otherwise oops on the CFAR access). It hasn't been tested enough to be confident that the CFAR values are actually accurate, but one thing at a time. Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pagesScott Wood2011-10-062-4/+5
| | | | | | | | | | | This definition is backward compatible with MAV=1.0 as long as the guest does not set reserved bits in MAS1/MAS4. Also, fix the shift in booke206_tlb_to_page_size -- it's the base that should be able to hold a 4G page size, not the shift count. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: booke206: add "info tlb" supportScott Wood2011-10-062-0/+90
| | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* kvm: ppc: booke206: use MMU APIScott Wood2011-10-062-0/+87
| | | | | | | | | Share the TLB array with KVM. This allows us to set the initial TLB both on initial boot and reset, is useful for debugging, and could eventually be used to support migration. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Enable to use PAPR with PR style KVMAlexander Graf2011-10-062-0/+45
| | | | | | | | | | | | | | | | | | | | | | When running PR style KVM, we need to tell the kernel that we want to run in PAPR mode now. This means that we need to pass some more register information down and enable papr mode. We also need to align the HTAB to htab_size boundary. Using this patch, -M pseries works with kvm even on non-hv kvm implementations, as long as the preceding kernel patches are in. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - match on CONFIG_PSERIES v2 -> v3: - remove HIOR pieces from PAPR patch (ABI breakage)
* PPC: KVM: Add stubs for kvm helper functionsAlexander Graf2011-10-061-0/+26
| | | | | | | | | | | | | | We have a bunch of helper functions that don't have any stubs for them in case we don't have CONFIG_KVM enabled. That didn't bite us so far, because gcc can optimize them out pretty well, but we should really provide them. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - use uint64_t for clockfreq
* PPC: KVM: Remove kvmppc_read_host_propertyAlexander Graf2011-10-062-46/+0
| | | | | | | We just got rid of the last user of kvmppc_read_host_property, so we can now safely remove it. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: KVM: Add generic function to read host clockfreqAlexander Graf2011-10-062-0/+68
| | | | | | | | | | | | | We need to find out the host's clock-frequency when running on KVM, so let's export a respective function. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - enable 64bit values
* PPC: bamboo: Move host fdt copy to targetAlexander Graf2011-10-062-31/+0
| | | | | | | We have some code in generic kvm_ppc.c that is only used by 440. Move to the 440 specific device code. Signed-off-by: Alexander Graf <agraf@suse.de>
* softmmu_header: pass CPUState to tlb_fillBlue Swirl2011-10-011-4/+3
| | | | | | | Pass CPUState pointer to tlb_fill() instead of architecture local cpu_single_env hacks. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* core: remove qemu_service_ioFrediano Ziglio2011-09-231-1/+1
| | | | | | | | | qemu_service_io was mainly an alias to qemu_notify_event, currently used only by PPC for timer hack, so call qemu_notify_event directly. Signed-off-by: Frediano Ziglio <freddy77@gmail.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Remove blanks before \n in output stringsStefan Weil2011-09-161-1/+1
| | | | | | | | | | | | | | Those blanks violate the coding conventions, see scripts/checkpatch.pl. Blanks missing after colons in the changed lines were added. This patch does not try to fix tabs, long lines and other problems in the changed lines, therefore checkpatch.pl reports many violations. Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* PPC: E500: Set ESR valuesAlexander Graf2011-08-231-0/+6
| | | | | | | | | When an exception occurs on BookE, we need to set ESR bits to expose to the guest information on what exactly happened. Add the obvious ones. Reported-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* PPC: E500: Inject SPE exception on invalid SPE accessAlexander Graf2011-08-231-39/+39
| | | | | | | | | | When accessing an SPE instruction despite it being not available, throw an SPE exception instead of an APU exception. That way the guest knows what's going on and actually uses SPE. Reported-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* PPC: E500: Add ESR bit definitionsAlexander Graf2011-08-232-3/+18
| | | | | | | | | The BookE spec specifies a number of ESR bits. Add defines for them so we can use them later on. Reported-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* Use glib memory allocation and free functionsAnthony Liguori2011-08-203-6/+6
| | | | | | qemu_malloc/qemu_free no longer exist after this commit. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl2011-08-073-4/+4
| | | | | | | | | Parameter is_softmmu (and its evil mutant twin brother is_softmuu) is not used in cpu_*_handle_mmu_fault() functions, remove them and adjust callers. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Avoid allocating TCG resources in non-TCG modeJan Kiszka2011-08-051-1/+3
| | | | | | | | | Do not allocate TCG-only resources like the translation buffer when running over KVM or XEN. Saves a "few" bytes in the qemu address space and is also conceptually cleaner. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* exec.h cleanupBlue Swirl2011-07-302-35/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move softmmu_exec.h include directives from target-*/exec.h to target-*/op_helper.c. Move also various other stuff only used in op_helper.c there. Define global env in dyngen-exec.h. For i386, move wrappers for segment and FPU helpers from user-exec.c to op_helper.c. Implement raise_exception_err_env() to handle dynamic CPUState. Move the function declarations to cpu.h since they can be used outside of op_helper.c context. LM32, s390x, UniCore32: remove unused cpu_halted(), regs_to_env() and env_to_regs(). ARM: make raise_exception() static. Convert #include "exec.h" to #include "cpu.h" #include "dyngen-exec.h" and remove now unused target-*/exec.h. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-alpha, target-ppc: Remove unnecessary setjmp.h includePeter Maydell2011-07-121-2/+0
| | | | | | | | | | Remove the include of setjmp.h from the cpu.h of target-alpha and target-ppc. This is unnecessary because cpu-defs.h already includes this header; this change brings these two targets into line with all the rest. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafBlue Swirl2011-07-016-176/+284
|\ | | | | | | | | | | | | | | | | | | | | | | | | * 'ppc-next' of git://repo.or.cz/qemu/agraf: PPC: move TLBs to their own arrays PPC: 440: Use 440 style MMU as default, so Qemu knows the MMU type PPC: E500: Use MAS registers instead of internal TLB representation PPC: Only set lower 32bits with mtmsr PPC: update openbios firmware PPC: mpc8544ds: Add hypervisor node PPC: calculate kernel,initrd,cmdline locations dynamically target-ppc: Handle memory-forced I/O controller access PPC: E500: Implement reboot controller
| * PPC: move TLBs to their own arraysAlexander Graf2011-06-175-35/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Until now, we've created a union over multiple different TLB types and allocated that union. While it's a waste of memory (and cache) to allocate TLB information for a TLB type with much information when you only need little, it also inflicts another issue. With the new KVM API, we can now share the TLB between KVM and qemu, but for that to work we need to have both be in the same layout. We can't just stretch it over to fit some internal different TLB representation. Hence this patch moves all TLB types to their own array, allowing us to only address and allocate exactly the boundaries required for the specific TLB type at hand. Signed-off-by: Alexander Graf <agraf@suse.de>
| * PPC: E500: Use MAS registers instead of internal TLB representationAlexander Graf2011-06-173-135/+200
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The natural format for e500 cores to do TLB manipulation with are the MAS registers. Instead of converting them into some internal representation and back again when the guest reads them, we can just keep the data identical to the way the guest passed it to us. The main advantage of this approach is that we're getting closer to being able to share MMU data with KVM using shared memory, so that we don't need to copy lots of MMU data back and forth all the time. For this to work however, another patch is required that gets rid of the TLB union, as that destroys our memory layout that needs to be identical with the kernel one. Signed-off-by: Alexander Graf <agraf@suse.de>
| * PPC: Only set lower 32bits with mtmsrAlexander Graf2011-06-171-11/+6
| | | | | | | | | | | | | | | | | | | | | | As Nathan pointed out correctly, the mtmsr instruction does not modify the high 32 bits of MSR. It also doesn't matter if SF is set or not, the instruction always behaves the same. This patch moves it a bit closer to the spec. Reported-by: Nathan Whitehorn <nwhitehorn@freebsd.org> Signed-off-by: Alexander Graf <agraf@suse.de>
| * target-ppc: Handle memory-forced I/O controller accessHervé Poussineau2011-06-171-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On at least the PowerPC 601, a direct-store (T=1) with bus unit ID 0x07F is special-cased as memory-forced I/O controller access. It is supposed to be checked immediately if T=1, bypassing all protection mechanisms and acting cache-inhibited and global. Signed-off-by: Hervé Poussineau <hpoussin@reactos.org> Simplified by avoiding reindentation. Added explanatory comments. Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* | Remove exec-all.h include directivesBlue Swirl2011-06-263-3/+0
| | | | | | | | | | | | Most exec-all.h include directives are now useless, remove them. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | Move cpu_has_work and cpu_pc_from_tb to cpu.hBlue Swirl2011-06-262-11/+12
| | | | | | | | | | | | | | Move functions cpu_has_work() and cpu_pc_from_tb() from exec.h to cpu.h. This is needed by later patches. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | exec.h: fix coding style and change cpu_has_work to return boolBlue Swirl2011-06-261-2/+2
| | | | | | | | | | | | | | | | | | Before the next patch, fix coding style of the areas affected. Change the type of the return value from cpu_has_work() and qemu_cpu_has_work() to bool. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | cpu_loop_exit: avoid using AREG0Blue Swirl2011-06-261-1/+1
| | | | | | | | | | | | | | Make cpu_loop_exit() take a parameter for CPUState instead of relying on global env. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* | kvm: ppc: Drop KVM_CAP build dependenciesJan Kiszka2011-06-201-14/+0
| | | | | | | | | | | | | | | | | | No longer needed with accompanied kernel headers. CC: Alexander Graf <agraf@suse.de> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* | kvm: ppc: Drop CONFIG_KVM_PPC_PVRJan Kiszka2011-06-201-9/+0
|/ | | | | | | | | Required header support is now unconditionally available. CC: Alexander Graf <agraf@suse.de> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* Fix compilation warning due to missing header for sigaction (followup)Alexandre Raymond2011-06-081-1/+0
| | | | | | | | This patch removes all references to signal.h when qemu-common.h is included as they become redundant. Signed-off-by: Alexandre Raymond <cerbere@gmail.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafAurelien Jarno2011-06-032-12/+10
|\ | | | | | | | | | | | | | | | | * 'ppc-next' of git://repo.or.cz/qemu/agraf: PPC: fix mpc8544ds pci default devices Fix segfault on screendump with -nographic PPC: install mpc8544ds.dtb PPC: fix sregs usage on booke ppc: Fix compilation for ppc64-softmmu
| * PPC: fix sregs usage on bookeAlexander Graf2011-06-031-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compiling qemu with kvm support on BookE PPC machines, I get the following error: cc1: warnings being treated as errors /tmp/qemu/target-ppc/kvm.c: In function 'kvm_arch_get_registers': /tmp/qemu/target-ppc/kvm.c:188: error: unused variable 'sregs' This is due to overly ambitious #ifdef'ery introduced in 90dc88. Fix it by keeping code that doesn't depend on new headers alive for the compiler, but never executed due to failing capability checks. CC: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
| * ppc: Fix compilation for ppc64-softmmuStefan Weil2011-06-031-6/+6
| | | | | | | | | | | | | | | | | | | | | | When QEMU was configured with --enable-debug-tcg, compilation fails in spr_write_booke206_mmucsr0() and in spr_write_booke_pid(). Similar changes are also needed in conditional code which is normally unused. Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* | target-ppc: remove old CONFIG_SOFTFLOAT #ifdefAurelien Jarno2011-06-033-15/+0
|/ | | | | | | | | target-ppc has been switched to softfloat only long ago, but a few #ifdef CONFIG_SOFTFLOAT have been forgotten. Remove them. Cc: Alexander Graf <agraf@suse.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Merge branch 'trivial-patches' of git://repo.or.cz/qemu/stefanhaAurelien Jarno2011-05-231-1/+1
|\ | | | | | | | | | | | | | | * 'trivial-patches' of git://repo.or.cz/qemu/stefanha: Fix typos in comments (chek -> check) hw/sd.c: Don't complain about SDIO commands CMD52/CMD53 hw/realview.c: Remove duplicate #include line piix_pci: fix piix3_set_irq_pic()
| * Fix typos in comments (chek -> check)Stefan Weil2011-05-221-1/+1
| | | | | | | | | | Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* | Merge branch 'ppc-next' of git://repo.or.cz/qemu/agrafAurelien Jarno2011-05-232-7/+6
|\ \ | |/ |/| | | | | | | | | * 'ppc-next' of git://repo.or.cz/qemu/agraf: Fix a bug in mtsr/mtsrin emulation on ppc64 pSeries: Clean up write-only variables w32: Fix compilation and replace non-portable usage of ulong
| * Fix a bug in mtsr/mtsrin emulation on ppc64David Gibson2011-05-201-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Early ppc64 CPUs include a hack to partially simulate the ppc32 segment registers, by translating writes to them into writes to the SLB. This is not used by any current Linux kernel, but it is used by the openbios used in the qemu mac99 model. Commit 81762d6dd0d430d87024f2c83e9c4dcc4329fb7d, cleaning up the SLB handling introduced a bug in this code, breaking the openbios currently in qemu. Specifically, there was an off by one error bitshuffling the register format used by mtsr into the format needed for the SLB load, causing the flag bits to end up in the wrong place. This caused the storage keys to be wrong under openbios, meaning that the translation code incorrectly thought a legitimate access was a permission violation. This patch fixes the bug, at the same time it fixes some build bug in the MMU debugging code (only exposed when DEBUG_MMU is enabled). Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
| * w32: Fix compilation and replace non-portable usage of ulongStefan Weil2011-05-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | ulong is undefined for w32 (and maybe other) compilations. Replace it by uintptr_t (which also fixes compilation for w64 and is a better choice for pointer to integer conversions). Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* | Delete unused tb_invalidate_page_rangeBlue Swirl2011-05-221-1/+0
|/ | | | | | | | | | | | tb_invalidate_page_range() was intended to be used to invalidate an area of a TB which the guest explicitly flushes from i-cache. However, QEMU detects writes to code areas where TBs have been generated, so his has never been useful. Delete the function, adjust callers. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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