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* target-ppc: Remove PVR check from migrationAlexey Kardashevskiy2014-06-161-2/+6
| | | | | | | | | | | | | | | | | | | | | | Currently migration fails if CPU version (PVR register) is different even a bit. This check is performed at the very end of migration when device states are sent. This is too late for management software and we need to provide a way for the user to make sure that migration will succeed if QEMU is started with appropritate command line parameters. This removes the PVR check. This resets PVR to the default value as the existing VMSTATE record for SPR array sends all 1024 registers unconditionally and overwrites the destination PVR. If the user wants some guarantees for migration to succeed, then a CPU name or "host" CPU with a "compat" option (on its way to upsteam) should be used and KVM or TCG is expected to fail on unsupported values at the moment of QEMU start. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Eliminate Magic Number MSR MasksTom Musta2014-06-161-54/+776
| | | | | | | | | | | | | | | | | Use MSR mnemonics from cpu.h instead of magic numbers for the CPUPPCState.msr_mask initialization. There is one bit in the 401x2 (and subsequent) model that I could not find any documentation for. It is open coded at little endian bit position 20: pcc->msr_mask = (1ull << 20) | (1ull << MSR_KEY) | (1ull << MSR_POW) | (1ull << MSR_CE) | ... Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Remove redundant POWER7 declarationsAlexey Kardashevskiy2014-06-162-6/+0
| | | | | | | | | | | | At the moment there are 3 versions of POWER7 CPUs defined. However we do not emulate these CPUs diffent and it does not make much sense to keep them all. This removes POWER7_v2.0 and POWER7_v2.1 and leaves just one versioned CPU per family which is POWER7_v2.3 with POWER7 alias. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Move alias lookup after class lookupAlexey Kardashevskiy2014-06-161-7/+11
| | | | | | | | | This moves aliases lookup after CPU class lookup. This is to let new generic CPU to be found first if it is present and only if it is not (TCG case), use aliases. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Create versionless CPU class per family if KVMAlexey Kardashevskiy2014-06-161-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | At the moment generic version-less CPUs are supported via hardcoded aliases. For example, POWER7 is an alias for POWER7_v2.1. So when QEMU is started with -cpu POWER7, the POWER7_v2.1 class instance is created. This approach works for TCG and KVMs other than HV KVM. HV KVM cannot emulate PVR value so the guest always sees the real PVR. HV KVM will not allow setting PVR other that the host PVR because of that (the kernel patch for it is on its way). So in most cases it is impossible to run QEMU with -cpu POWER7 unless the host PVR is exactly the same as the one from the alias (which is now POWER7_v2.3). It was decided that under HV KVM QEMU should use -cpu host. Using "host" CPU type creates a problem for management tools such as libvirt because they want to know in advance if the destination guest can possibly run on the destination. Since the "host" type is really not a type and will always work with any KVM, there is no way for libvirt to know if the migration will success. This registers additional CPU class derived from the host CPU family. The name for it is taken from @desc field of the CPU family class. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: gdbstub allow byte swapping for reading/writing registersThomas Falcon2014-06-161-0/+19
| | | | | | | | | | This patch allows registers to be properly read from and written to when using the gdbstub to debug a ppc guest running in little endian mode. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Thomas Falcon <tlfalcon@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: extract register length calculation in gdbstubThomas Falcon2014-06-161-34/+71
| | | | | | | | | This patch extracts the method to determine a register's size into a separate function. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Thomas Falcon <tlfalcon@linux.vnet.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* savevm: Remove all the unneeded version_minimum_id_old (ppc)Juan Quintela2014-06-161-25/+13
| | | | | | | | | | | | | | | | | | | | After previous Peter patch, they are redundant. This way we don't assign them except when needed. Once there, there were lots of case where the ".fields" indentation was wrong: .fields = (VMStateField []) { and .fields = (VMStateField []) { Change all the combinations to: .fields = (VMStateField[]){ The biggest problem (appart from aesthetics) was that checkpatch complained when we copy&pasted the code from one place to another. Signed-off-by: Juan Quintela <quintela@redhat.com> Acked-by: Alexey Kardashevskiy <aik@ozlabs.ru>
* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-054-6/+4
| | | | | | | | | | This will collect all load and store helpers soon. For now it is just a replacement for softmmu_exec.h, which this patch stops including directly, but we also include it where this will be necessary in order to simplify the next patch. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: commonize helper definitionsPaolo Bonzini2014-06-051-14/+0
| | | | | | | | | They do not need to be in op_helper.c. Because cputlb.c now includes softmmu_template.h twice for each size, io_readX must be elided the second time through. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-2811-16/+11
| | | | | | | | | | Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* cpu: make CPU_INTERRUPT_RESET available on all targetsPaolo Bonzini2014-05-131-3/+0
| | | | | | | | | | | | | | | | On the x86, some devices need access to the CPU reset pin (INIT#). Provide a generic service to do this, using one of the internal cpu_interrupt targets. Generalize the PPC-specific code for CPU_INTERRUPT_RESET to other targets. Since PPC does not support migration across QEMU versions (its machine types are not versioned yet), I picked the value that is used on x86, CPU_INTERRUPT_TGT_INT_1. Consequently, TGT_INT_2 and TGT_INT_3 are shifted down by one while keeping their value. Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* kvm: reset state from the CPU's reset methodPaolo Bonzini2014-05-131-4/+0
| | | | | | | | | | | | | | | | | | | Now that we have a CPU object with a reset method, it is better to keep the KVM reset close to the CPU reset. Using qemu_register_reset as we do now keeps them far apart. With this patch, PPC no longer calls the kvm_arch_ function, so it can get removed there. Other arches call it from their CPU reset handler, and the function gets an ARMCPU/X86CPU/S390CPU. Note that ARM- and s390-specific functions are called kvm_arm_* and kvm_s390_*, while x86-specific functions are called kvm_arch_*. That follows the convention used by the different architectures. Changing that is the topic of a separate patch. Reviewed-by: Gleb Natapov <gnatapov@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* ppc: use kvm_vcpu_enable_cap()Cornelia Huck2014-04-301-17/+4
| | | | | | | | Convert existing users of KVM_ENABLE_CAP to new helper. Reviewed-by: Thomas Huth <thuth@linux.vnet.ibm.com> Reviewed-by: Alexander Graf <agraf@suse.de> Signed-off-by: Cornelia Huck <cornelia.huck@de.ibm.com>
* PPC: Add l1 cache sizes for 970 and above systemsAlexander Graf2014-04-081-0/+8
| | | | | | | | | Book3s_64 guests expect the L1 cache size in device tree, so let's give them proper values for all CPU types we support. This fixes a "not compliant" warning with sles11 guests on -M pseries for me. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Only enter MSR_POW when no interrupts pendingAlexander Graf2014-04-081-1/+1
| | | | | | | | | | We were entering the power saving state even when interrupts (like an external interrupt or a decrementer interrupt) were still in flight. In case we find a pending interrupt, don't enter power saving state. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Tom Musta <tmusta@gmail.com>
* PPC: Clean up DECR implementationAlexander Graf2014-04-082-2/+4
| | | | | | | | | | | | | | | | | | | There are 3 different variants of the decrementor for BookE and BookS. The BookE variant sets TSR[DIS] to 1 when the DEC value becomes 1 or 0. TSR[DIS] is then the indicator whether the decrementor interrupt line is asserted or not. The old BookS variant treats DEC as an edge interrupt that gets triggered when the DEC value's top bit turns 1 from 0. The new BookS variant maintains the assertion bit inside DEC itself. Whenever the DEC value becomes negative (top bit set) the DEC interrupt line is asserted. So far we implemented mostly the old BookS variant. Let's do them all properly. This fixes booting pseries ppc64 guest images in TCG mode for me. Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Correct VSX Integer to FP ConversionTom Musta2014-04-081-24/+13
| | | | | | | | | | | This patch corrects the VSX integer to floating point conversion instructions by using the endian correct accessors. The auxiliary "j" index used by the existing macros is now obsolete and is removed. The JOFFSET preprocessor macro is also obsolete and removed. Signed-off-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Correct VSX FP to Integer ConversionTom Musta2014-04-081-21/+15
| | | | | | | | | | This patch corrects the VSX floating point to integer conversion instructions by using the endian correct accessors. The auxiliary "j" index used by the existing macros is now obsolete and is removed. Signed-off-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Correct VSX FP to FP ConversionsTom Musta2014-04-081-5/+4
| | | | | | | | | | | This change corrects the VSX double precision to single precision and single precision to double precisions conversion routines. The endian correct accessors are now used. The auxiliary "j" index is no longer necessary and is eliminated. Signed-off-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Correct VSX Scalar ComparesTom Musta2014-04-081-6/+7
| | | | | | | | | This change fixes the VSX scalar compare instructions. The existing usage of "x.f64[0]" is changed to "x.VsrD(0)". Signed-off-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Correct Simple VSR LE Host InversionsTom Musta2014-04-081-190/+190
| | | | | | | | | | | | | | | | | | | | | | | A common pattern in the VSX helper code macros is the use of "x.fld[i]" where "x" is a VSR and "fld" is an argument to a macro ("f64" or "f32" is passed). This is not always correct on LE hosts. This change addresses all instances of this pattern to be "x.fld" where "fld" is: - "VsrD(0)" for scalar instructions accessing 64-bit numbers - "VsrD(i)" for vector instructions accessing 64-bit numbers - "VsrW(i)" for vector instructions accessing 32-bit numbers Note that there are no instances of this pattern where a scalar instruction accesses a 32-bit number. Note also that it would be correct to use "VsrD(i)" for scalar instructions since the loop index is only ever "0". I have choosen to use "VsrD(0)" instead ... it seems a little clearer. Signed-off-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Correct LE Host Inversion of Lower VSRsTom Musta2014-04-081-4/+4
| | | | | | | | | | | This change properly orders the doublewords of the VSRs 0-31. Because these registers are constructed from separate doublewords, they must be inverted on Little Endian hosts. The inversion is performed both when the VSR is read and when it is written. Signed-off-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Define Endian-Correct Accessors for VSR Field AccessTom Musta2014-04-081-0/+8
| | | | | | | | | | | | | | | | | | | | This change defines accessors for VSR doubleword and word fields that are correct from a host Endian perspective. This allows code to use the Power ISA indexing numbers in code. For example, the xscvdpsxws instruction has a target VSR that looks like this: 0 32 64 127 +-----------+--------+-----------+-----------+ | undefined | SW | undefined | undefined | +-----------+--------+-----------+-----------+ VSX helper code will use VsrW(1) to access this field. Signed-off-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Bug: VSX Convert to Integer Should TruncateTom Musta2014-04-081-1/+2
| | | | | | | | | | | | | | The various VSX Convert to Integer instructions should truncate the floating point number to an integer value, which is equivalent to a round-to-zero rounding mode. The existing VSX floating point to integer conversion helpers are erroneously using the rounding mode set int the PowerPC Floating Point Status and Control Register (FPSCR). This change corrects this defect by using the appropriate float*_to_*_round_to_zero() routines fro the softfloat library. Signed-off-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: MSR_POW not supported on POWER7/7+/8Anton Blanchard2014-03-271-3/+3
| | | | | | | | | Remove MSR_POW from the msr_mask for POWER7/7P/8. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Cédric Le Goater <clg@fr.ibm.com> Tested-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: POWER7+ supports the MSR_VSX bitAnton Blanchard2014-03-271-1/+1
| | | | | | | | | Without MSR_VSX we die early during a Linux boot. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Cédric Le Goater <clg@fr.ibm.com> Tested-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: POWER8 supports iselAnton Blanchard2014-03-271-1/+1
| | | | | | | | | Add PPC_ISEL to insns_flags. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Cédric Le Goater <clg@fr.ibm.com> Tested-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: POWER8 supports the MSR_LE bitAnton Blanchard2014-03-271-1/+1
| | | | | | | | | Add MSR_LE to the msr_mask for POWER8. Signed-off-by: Anton Blanchard <anton@samba.org> Reviewed-by: Cédric Le Goater <clg@fr.ibm.com> Tested-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Introduce powerisa-207-server flagAlexey Kardashevskiy2014-03-202-1/+4
| | | | | | | | | | | | This flag will be used to decide whether to emulate some bits of H_SET_MODE hypercall because some are POWER8-only. While we are here, add 2.05 flag to POWER8 family too. POWER7/7+ already have it. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Force CPU threads count to be a power of 2Bharata B Rao2014-03-201-0/+6
| | | | | | | | | | | | | | PowerPC kernel expects the number of SMT threads in a core to be a power of 2. Since QEMU doesn't enforce this, it leads to an early guest kernel crash if invalid threads count is specified. Prevent this crash and make it a graceful exit from QEMU itself by validating the user-supplied threads count. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Eric Blake <eblake@redhat.com> Reviewed-by: Stewart Smith <stewart@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Fix overallocation of opcode tablesStuart Brady2014-03-201-1/+1
| | | | | | | | | | create_new_table() should allocate 0x20 opc_handler_t pointers, but actually allocates 0x20 opc_handler_t structs. Fix this. Signed-off-by: Stuart Brady <sdb@zubnet.me.uk> Reviewed-by: Tom Musta <tommusta@gmail.com> Tested-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Reset SPRs on CPU resetAlexey Kardashevskiy2014-03-202-1/+12
| | | | | | | | | This resets SPR values to defaults on CPU reset. This should help with little-endian guests reboot issues. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Greg Kurz <gkurz@linux.vnet.ibm.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Add missing 'static' and 'const' attributesStefan Weil2014-03-193-6/+6
| | | | | | | This fixes warnings from the static code analysis (smatch). Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Andreas Färber <afaerber@suse.de>
* misc: Fix typos in commentsStefan Weil2014-03-151-1/+1
| | | | | | | | | | | | | | | Codespell found and fixed these new typos: * doesnt -> doesn't * funtion -> function * perfomance -> performance * remaing -> remaining A coding style issue (line too long) was fixed manually. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber2014-03-133-7/+7
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cputlb: Change tlb_flush() argument to CPUStateAndreas Färber2014-03-136-23/+39
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber2014-03-131-25/+33
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* exec: Change cpu_abort() argument to CPUStateAndreas Färber2014-03-135-53/+62
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Use PowerPCCPU in PowerPCCPUClass::handle_mmu_fault hookAndreas Färber2014-03-136-10/+14
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | | | This lets us drop some local variables in tlb_fill() functions. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* exec: Change tlb_fill() argument to CPUStateAndreas Färber2014-03-131-4/+5
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-2/+2
| | | | | | | | Most targets were using offsetof(CPUFooState, breakpoints) to determine how much of CPUFooState to clear on reset. Use the next field after CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber2014-03-138-58/+75
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber2014-03-133-5/+9
| | | | | | | | Note that while such functions may exist both for *-user and softmmu, only *-user uses the CPUState hook, while softmmu reuses the prototype for calling it directly. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Factor out cpu_generic_init()Andreas Färber2014-03-131-20/+1
| | | | | | | All targets using it gain the ability to set -cpu name,key=value,... options via the default TYPE_CPU CPUClass::parse_features() implementation. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2014-03-132-8/+9
| | | | | | | | | Default to false. Tidy variable naming and inline cast uses while at it. Tested-by: Jia Liu <proljc@gmail.com> (or32) Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Clean up ENV_GET_CPU() usageAndreas Färber2014-03-133-7/+13
| | | | | | | | | | | | | | Commits fdfba1a298ae26dd44bcfdb0429314139a0bc55a, ab1da85791340e504d10487e1add81b9988afa98, f606604f1c10b60ef294f1b9b229426521a365e3 and 2c17449b3022ca9623c4a7e2a504a4150ac4ad30 added usages of ENV_GET_CPU() macro in target-specific code. Use ppc_env_get_cpu() instead. Cc: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: spapr: e500: fix to use cpu_dt_idAlexey Kardashevskiy2014-03-052-1/+2
| | | | | | | | | | | | | | | | | This makes use of @cpu_dt_id and related API in: 1. emulated XICS hypercall handlers as they receive fixed CPU indexes; 2. XICS-KVM to enable in-kernel XICS on right CPU; 3. device-tree renderer. This removes @cpu_index fixup as @cpu_dt_id is used instead so QEMU monitor can accept command-line CPU indexes again. This changes kvm_arch_vcpu_id() to use ppc_get_vcpu_dt_id() as at the moment KVM CPU id and device tree ID are calculated using the same algorithm. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Acked-by: Mike Day <ncmike@ncultra.org> Signed-off-by: Alexander Graf <agraf@suse.de>
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