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* target-ppc/fpu_helper: fix FPSCR_FX bit shift operationMadhavan Srinivasan2015-11-301-11/+11
| | | | | | | | | | | Currently in TCG mode, updating floating exception summary bit (FPSCR_FX) in fpscr also updates the upper 32bits of fpscr with all 1s. Modify the bit shift operation statement to use 1ULL instead. Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target-ppc: Move the FPSCR bit update macros to cpu.hMadhavan Srinivasan2015-11-302-21/+21
| | | | | | | | Move the FPSCR bit update macros defined in dfp_helper to cpu.h. This way, fpu_helper functions can also use them Signed-off-by: Madhavan Srinivasan <maddy@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* monitor/target-ppc: Define target_get_monitor_defAlexey Kardashevskiy2015-11-122-172/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment get_monitor_def() returns only registers from statically defined monitor_defs array. However there is a lot of BOOK3S SPRs which are not in the list and cannot be printed from the monitor. This adds a new target platform hook - target_get_monitor_def(). The hook is called if a register was not found in the static array returned by the target_monitor_defs() hook. The hook is only defined for POWERPC, it returns registered SPRs and fails on unregistered ones providing the user with information on what is actually supported on the running CPU. The register value is saved as uint64_t as it is the biggest supported register size; target_ulong cannot be used because of the stub - it is in a "common" code and cannot include "cpu.h", etc; this is also why the hook prototype is redefined in the stub instead of being included from some header. This replaces static descriptors for GPRs, FPRs, SRs with a helper which looks for a value in a corresponding array in the CPUPPCState. The immediate effect is that all 32 SRs can be printed now (instead of 16); later this can be reused for VSX or TM registers. This replaces callbacks for MSR and XER with static descriptors in monitor_defs as they are stored in CPUPPCState. While we are here, this adds "cr" as a synonym of "ccr". Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* PPC: Fix lswx bounds checksAlexander Graf2015-11-121-2/+3
| | | | | | | | | | | | | The lswx instruction checks whether the desired string actually fits into all defined registers. Unfortunately it does the calculation wrong, resulting in illegal instruction traps for loads that really should fit. Fix it up, making Mac OS happier. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* PPC: Allow Rc bit to be set on mtsprAlexander Graf2015-11-121-1/+1
| | | | | | | | | | | | | | | | According to the ISA setting the Rc bit on mtspr is undefined behavior. Real 750 hardware simply ignores the bit and doesn't touch cr0 though. Unfortunately, Mac OS 9 relies on this fact and executes a few mtspr instructions (to set XER for example) with Rc set. So let's handle the bit the same way hardware does and ignore it. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc: Let kvmppc_reset_htab() return 0 for !CONFIG_KVMBharata B Rao2015-11-111-1/+1
| | | | | | | | | | | The !CONFIG_KVM implementation of kvmppc_reset_htab() returns -1 by default. Change this to return 0 so that we fall back to user space HTAB allocation for emulated guests. This fixes the make check failures for ppc64 emulated target. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc: Add/Re-introduce MMU model definitions needed by PR KVMBharata B Rao2015-11-112-0/+14
| | | | | | | | | | | | | Commit aa4bb5875231 (ppc: Add mmu_model defines for arch 2.03 and 2.07) removed the mmu_model definition POWERPC_MMU_2_06a which is needed by PR KVM. Reintroduce it and also add POWERPC_MMU_2_07a. This fixes QEMU crash (qemu: fatal: Unknown MMU model) during booting of PR KVM guest. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* taget-ppc: Fix read access to IBAT registers higher than IBAT3Julio Guerra2015-11-061-1/+1
| | | | | | | | | | Fix the index used to read the IBAT's vector which results in IBAT0..3 instead of IBAT4..N. The bug appeared by saving/restoring contexts including IBATs values. Signed-off-by: Julio Guerra <julio@farjump.io> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* target-*: Advance pc after recognizing a breakpointRichard Henderson2015-10-281-0/+5
| | | | | | | | Some targets already had this within their logic, but make sure it's present for all targets. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* ppc/spapr: Add "ibm,pa-features" property to the device-treeBenjamin Herrenschmidt2015-10-233-0/+9
| | | | | | | | | | | | | | | | LoPAPR defines a "ibm,pa-features" per-CPU device tree property which describes extended features of the Processor Architecture. This adds the property to the device tree. At the moment this is the copy of what pHyp advertises except "I=1 (cache inhibited) Large Pages" which is enabled for TCG and disabled when running under HV KVM host with 4K system page size. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [aik: rebased, changed commit log, moved ci_large_pages initialization, renamed pa_features arrays] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* ppc: Add mmu_model defines for arch 2.03 and 2.07Benjamin Herrenschmidt2015-10-235-20/+22
| | | | | | | | | | | | | | | | | | This removes unused POWERPC_MMU_2_06a/POWERPC_MMU_2_06d. This replaces POWERPC_MMU_64B with POWERPC_MMU_2_03 for POWER5+ to be more explicit about the version of the PowerISA supported. This defines POWERPC_MMU_2_07 and uses it for the POWER8 CPU family. This will not have an immediate effect now but it will in the following patch. This should cause no behavioural change. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> [aik: rebased, changed commit log] Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* spapr_iommu: Rename vfio_accel parameterDavid Gibson2015-10-232-3/+3
| | | | | | | | | | | | | | | | | | The vfio_accel parameter used when creating a new TCE table (guest IOMMU context) has a confusing name. What it really means is whether we need the TCE table created to be able to support VFIO devices. VFIO is relevant, because when available we use in-kernel acceleration of the TCE table, but that may not work with VFIO devices because updates to the table are handled in kernel, bypass qemu and so don't hit qemu's infrastructure for keeping the VFIO host IOMMU state in sync with the guest IOMMU state. Rename the parameter to "need_vfio" throughout. This is a cosmetic change, with no impact on the logic. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <lvivier@redhat.com>
* kvm: Pass PCI device pointer to MSI routing functionsPavel Fedin2015-10-191-1/+1
| | | | | | | | | | | | | | | | | In-kernel ITS emulation on ARM64 will require to supply requester IDs. These IDs can now be retrieved from the device pointer using new pci_requester_id() function. This patch adds pci_dev pointer to KVM GSI routing functions and makes callers passing it. x86 architecture does not use requester IDs, but hw/i386/kvm/pci-assign.c also made passing PCI device pointer instead of NULL for consistency with the rest of the code. Signed-off-by: Pavel Fedin <p.fedin@samsung.com> Message-Id: <ce081423ba2394a4efc30f30708fca07656bc500.1444916432.git.p.fedin@samsung.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* qdev: Protect device-list-properties against broken devicesMarkus Armbruster2015-10-091-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several devices don't survive object_unref(object_new(T)): they crash or hang during cleanup, or they leave dangling pointers behind. This breaks at least device-list-properties, because qmp_device_list_properties() needs to create a device to find its properties. Broken in commit f4eb32b "qmp: show QOM properties in device-list-properties", v2.1. Example reproducer: $ qemu-system-aarch64 -nodefaults -display none -machine none -S -qmp stdio {"QMP": {"version": {"qemu": {"micro": 50, "minor": 4, "major": 2}, "package": ""}, "capabilities": []}} { "execute": "qmp_capabilities" } {"return": {}} { "execute": "device-list-properties", "arguments": { "typename": "pxa2xx-pcmcia" } } qemu-system-aarch64: /home/armbru/work/qemu/memory.c:1307: memory_region_finalize: Assertion `((&mr->subregions)->tqh_first == ((void *)0))' failed. Aborted (core dumped) [Exit 134 (SIGABRT)] Unfortunately, I can't fix the problems in these devices right now. Instead, add DeviceClass member cannot_destroy_with_object_finalize_yet to mark them: * Hang during cleanup (didn't debug, so I can't say why): "realview_pci", "versatile_pci". * Dangling pointer in cpus: most CPUs, plus "allwinner-a10", "digic", "fsl,imx25", "fsl,imx31", "xlnx,zynqmp", because they create such CPUs * Assert kvm_enabled(): "host-x86_64-cpu", host-i386-cpu", "host-powerpc64-cpu", "host-embedded-powerpc-cpu", "host-powerpc-cpu" (the powerpc ones can't currently reach the assertion, because the CPUs are only registered when KVM is enabled, but the assertion is arguably in the wrong place all the same) Make qmp_device_list_properties() fail cleanly when the device is so marked. This improves device-list-properties from "crashes, hangs or leaves dangling pointers behind" to "fails". Not a complete fix, just a better-than-nothing work-around. In the above reproducer, device-list-properties now fails with "Can't list properties of device 'pxa2xx-pcmcia'". This also protects -device FOO,help, which uses the same machinery since commit ef52358 "qdev-monitor: include QOM properties in -device FOO, help output", v2.2. Example reproducer: $ qemu-system-aarch64 -machine none -device pxa2xx-pcmcia,help Before: qemu-system-aarch64: .../memory.c:1307: memory_region_finalize: Assertion `((&mr->subregions)->tqh_first == ((void *)0))' failed. After: Can't list properties of device 'pxa2xx-pcmcia' Cc: "Andreas Färber" <afaerber@suse.de> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Anthony Green <green@moxielogic.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Jia Liu <proljc@gmail.com> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Michael Walle <michael@walle.cc> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Richard Henderson <rth@twiddle.net> Cc: qemu-ppc@nongnu.org Cc: qemu-stable@nongnu.org Signed-off-by: Markus Armbruster <armbru@redhat.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Message-Id: <1443689999-12182-10-git-send-email-armbru@redhat.com>
* target-ppc: Remove unnecessary variableShraddha Barke2015-10-081-2/+1
| | | | | | | Compress lines and remove the variable. Signed-off-by: Shraddha Barke <shraddha.6596@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-35/+5
| | | | | | | | | | It is no longer used, so tidy up everything reached by it. This includes the gen_opc_* arrays, the search_pc parameter and the inline gen_intermediate_code_internal functions. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-2/+3
| | | | | | | | | | The gen_opc_* arrays are already redundant with the data stored in the insn_start arguments. Transition restore_state_to_opc to use data from the latter. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-1/+5
| | | | | | | | Adjust all translators to respect it. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-*: Drop cpu_gen_code defineRichard Henderson2015-10-071-1/+0
| | | | | | | | This symbol no longer exists. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-*: Introduce and use cpu_breakpoint_testRichard Henderson2015-10-071-9/+5
| | | | | | | | | | | | Reduce the boilerplate required for each target. At the same time, move the test for breakpoint after calling tcg_gen_insn_start. Note that arm and aarch64 do not use cpu_breakpoint_test, but still move the inline test down after tcg_gen_insn_start. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-2/+2
| | | | | | | | This does tidy the icount test common to all targets. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-3/+2
| | | | | | | | | | While we're at it, emit the opcode adjacent to where we currently record data for search_pc. This puts gen_io_start et al on the "correct" side of the marker. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-071-1/+1
| | | | | | | | With an eye toward making it mandatory. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* ppc: Rename ELF_MACHINE to be PPC specificPeter Crosthwaite2015-09-251-2/+2
| | | | | | | | | | | | | | | | Rename ELF_MACHINE to be PPC specific. This is used as-is by the various PPC bootloaders and is locally defined to ELF_MACHINE in linux user in PPC specific ifdeffery. This removes another architecture specific definition from the global namespace (as desired by multi-arch). Cc: Alexander Graf <agraf@suse.de> Cc: qemu-ppc@nongnu.org Reviewed-by: Richard Henderson <rth@twiddle.net> Acked-By: Riku Voipio <riku.voipio@linaro.org> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* ppc/spapr: Implement H_RANDOM hypercall in QEMUThomas Huth2015-09-232-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The PAPR interface defines a hypercall to pass high-quality hardware generated random numbers to guests. Recent kernels can already provide this hypercall to the guest if the right hardware random number generator is available. But in case the user wants to use another source like EGD, or QEMU is running with an older kernel, we should also have this call in QEMU, so that guests that do not support virtio-rng yet can get good random numbers, too. This patch now adds a new pseudo-device to QEMU that either directly provides this hypercall to the guest or is able to enable the in-kernel hypercall if available. The in-kernel hypercall can be enabled with the use-kvm property, e.g.: qemu-system-ppc64 -device spapr-rng,use-kvm=true For handling the hypercall in QEMU instead, a "RngBackend" is required since the hypercall should provide "good" random data instead of pseudo-random (like from a "simple" library function like rand() or g_random_int()). Since there are multiple RngBackends available, the user must select an appropriate back-end via the "rng" property of the device, e.g.: qemu-system-ppc64 -object rng-random,filename=/dev/hwrng,id=gid0 \ -device spapr-rng,rng=gid0 ... See http://wiki.qemu-project.org/Features-Done/VirtIORNG for other example of specifying RngBackends. Signed-off-by: Thomas Huth <thuth@redhat.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* spapr: Enable in-kernel H_SET_MODE handlingAlexey Kardashevskiy2015-09-232-0/+10
| | | | | | | | | | | | | | | | | For setting debug watchpoints, sPAPR guests use H_SET_MODE hypercall. The existing QEMU H_SET_MODE handler does not support this but the KVM handler in HV KVM does. However it is not enabled. This enables the in-kernel H_SET_MODE handler which handles: - Completed Instruction Address Breakpoint Register - Watch point 0 registers. The rest is still handled in QEMU. Reported-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
* target-ppc: fix xscmpodp and xscmpudp decodingAurelien Jarno2015-09-201-2/+9
| | | | | | | | | | | | | | | The xscmpodp and xscmpudp instructions only have the AX, BX bits in there encoding, the lowest bit (usually TX) is marked as an invalid bit. We therefore can't decode them with GEN_XX2FORM, which decodes the two lowest bit. Introduce a new form GEN_XX2FORM, which decodes AX and BX and mark the lowest bit as invalid. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Tested-by: Richard W.M. Jones <rjones@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: fix vcipher, vcipherlast, vncipherlast and vpermxorAurelien Jarno2015-09-201-5/+14
| | | | | | | | | | | | | | | For vector instructions, the helpers get pointers to the vector register in arguments. Some operands might point to the same register, including the operand holding the result. When emulating instructions which access the vector elements in a non-linear way, we need to store the result in an temporary variable. This fixes openssl when emulating a POWER8 CPU. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Fix SRR0 when taking unaligned exceptionsAnton Blanchard2015-09-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are setting SRR0 to the instruction before the one causing the unaligned exception. A quick testcase: . = 0x100 .globl _start _start: /* Cause a 0x600 */ li 3,0x1 stwcx. 3,0,3 1: b 1b . = 0x600 1: b 1b Built into something we can load as a BIOS image: gcc -mbig -c test.S ld -EB -Ttext 0x0 -o test test.o objcopy -O binary test test.bin Run with: qemu-system-ppc64 -nographic -bios test.bin Shows an incorrect SRR0 (points at the li): SRR0 0000000000000100 With the patch we get the correct SRR0: SRR0 0000000000000104 Signed-off-by: Anton Blanchard <anton@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
* kvm_ppc: remove kvmppc_timer_hackPaolo Bonzini2015-09-203-44/+1
| | | | | | | | | | QEMU does have an I/O thread now, that can be interrupted at any time because the VCPU thread runs outside the iothread mutex. Therefore, the kvmppc_timer_hack is obsolete. Remove it. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* monitor: remove target-specific code from monitor.cPavel Butsykin2015-09-162-1/+256
| | | | | | | | | | | | | | Move target-specific code out of /monitor.c to /target-*/monitor.c, this will avoid code cluttering and using random ifdeffery. The solution is quite simple, but solves the issue of the separation of target-specific code from monitor. Signed-off-by: Pavel Butsykin <pbutsykin@virtuozzo.com> Signed-off-by: Denis V. Lunev <den@openvz.org> CC: Paolo Bonzini <pbonzini@redhat.com> CC: Peter Maydell <peter.maydell@linaro.org> Message-Id: <1441899541-1856-3-git-send-email-den@openvz.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2015-09-111-1/+1
| | | | | | | | | | | | | | | | | | This is set to true when the index is for an instruction fetch translation. The core get_page_addr_code() sets it, as do the SOFTMMU_CODE_ACCESS acessors. All targets ignore it for now, and all other callers pass "false". This will allow targets who wish to split the mmu index between instruction and data accesses to do so. A subsequent patch will do just that for PowerPC. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Message-Id: <1439796853-4410-2-git-send-email-benh@kernel.crashing.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* Target-ppc: Remove unnecessary variableShraddha Barke2015-09-111-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Compress lines and remove the variable ret. Change made using Coccinelle script @@ expression ret; @@ - if (ret) return ret; - return 0; + return ret; @@ local idexpression ret; expression e; @@ - ret = e; - return ret; + return e; @@ type T; identifier i; @@ - T i; ... when != i Signed-off-by: Shraddha Barke <shraddha.6596@gmail.com> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* cpu-exec: Purge all uses of ENV_GET_CPU()Peter Crosthwaite2015-07-091-1/+1
| | | | | | | | | | | | | | | | Remove un-needed usages of ENV_GET_CPU() by converting the APIs to use CPUState pointers and retrieving the env_ptr as minimally needed. Scripted conversion for target-* change: for I in target-*/cpu.h; do sed -i \ 's/\(^int cpu_[^_]*_exec(\)[^ ][^ ]* \*s);$/\1CPUState *cpu);/' \ $I; done Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Change cpu_exec_init() arg to cpu, not envPeter Crosthwaite2015-07-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The callers (most of them in target-foo/cpu.c) to this function all have the cpu pointer handy. Just pass it to avoid an ENV_GET_CPU() from core code (in exec.c). Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Anthony Green <green@moxielogic.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Blue Swirl <blauwirbel@gmail.com> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Move cpu_exec_init() call to realize functionBharata B Rao2015-07-091-2/+10
| | | | | | | | | | | | | | | | | Move cpu_exec_init() call from instance_init to realize. This allows any failures from cpu_exec_init() to be handled appropriately. Also add corresponding cpu_exec_exit() call from unrealize. cpu_dt_id assignment from instance_init is no longer needed since correct assignment for cpu_dt_id is already present in realizefn. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> [AF: Keep calling cpu_exec_init() for CONFIG_USER_ONLY] Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Add Error argument to cpu_exec_init()Bharata B Rao2015-07-091-1/+1
| | | | | | | | | | | | | | | | | | | | Add an Error argument to cpu_exec_init() to let users collect the error. This is in preparation to change the CPU enumeration logic in cpu_exec_init(). With the new enumeration logic, cpu_exec_init() can fail if cpu_index values corresponding to max_cpus have already been handed out. Since all current callers of cpu_exec_init() are from instance_init, use error_abort Error argument to abort in case of an error. Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Reviewed-by: Igor Mammedov <imammedo@redhat.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Acked-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into stagingPeter Maydell2015-07-081-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bugfixes and Daniel Berrange's crypto library. # gpg: Signature made Wed Jul 8 12:12:29 2015 BST using RSA key ID 78C7AE83 # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" # gpg: WARNING: This key is not certified with sufficiently trusted signatures! # gpg: It is not certain that the signature belongs to the owner. # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * remotes/bonzini/tags/for-upstream: ossaudio: fix memory leak ui: convert VNC to use generic cipher API block: convert qcow/qcow2 to use generic cipher API ui: convert VNC websockets to use crypto APIs block: convert quorum blockdrv to use crypto APIs crypto: add a nettle cipher implementation crypto: add a gcrypt cipher implementation crypto: introduce generic cipher API & built-in implementation crypto: move built-in D3DES implementation into crypto/ crypto: move built-in AES implementation into crypto/ crypto: introduce new module for computing hash digests vl: move rom_load_all after machine init done Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * crypto: move built-in AES implementation into crypto/Daniel P. Berrange2015-07-071-1/+1
| | | | | | | | | | | | | | | | | | To prepare for a generic internal cipher API, move the built-in AES implementation into the crypto/ directory Signed-off-by: Daniel P. Berrange <berrange@redhat.com> Message-Id: <1435770638-25715-3-git-send-email-berrange@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | target-ppc: fix hugepage support when using memory-backend-fileMichael Roth2015-07-071-6/+51
|/ | | | | | | | | | | | | | | | | | | | | | | | Current PPC code relies on -mem-path being used in order for hugepage support to be detected. With the introduction of MemoryBackendFile we can now handle this via: -object memory-file-backend,mem-path=...,id=hugemem0 \ -numa node,id=mem0,memdev=hugemem0 Management tools like libvirt treat the 2 approaches as interchangeable in some cases, which can lead to user-visible regressions even for previously supported guest configurations. Fix these by also iterating through any configured memory backends that may be backed by hugepages. Since the old code assumed hugepages always backed the entirety of guest memory, play it safe an pick the minimum across the max pages sizes for all backends, even ones that aren't backed by hugepages. Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* kvm: First step to push iothread lock out of inner run loopJan Kiszka2015-07-011-0/+7
| | | | | | | | | | | | | | | | | | | This opens the path to get rid of the iothread lock on vmexits in KVM mode. On x86, the in-kernel irqchips has to be used because we otherwise need to synchronize APIC and other per-cpu state accesses that could be changed concurrently. Regarding pre/post-run callbacks, s390x and ARM should be fine without specific locking as the callbacks are empty. MIPS and POWER require locking for the pre-run callback. For the handle_exit callback, it is non-empty in x86, POWER and s390. Some POWER cases could do without the locking, but it is left in place for now. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Message-Id: <1434646046-27150-7-git-send-email-pbonzini@redhat.com>
* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | disas does not need to access the CPU env for any reason. Change the APIs to accept CPU pointers instead. Small change pattern needs to be applied to all target translate.c. This brings us closer to making disas.o a common-obj and less architecture specific in general. Cc: Richard Henderson <rth@twiddle.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Eduardo Habkost <ehabkost@redhat.com> Cc: Michael Walle <michael@walle.cc> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Leon Alrae <leon.alrae@imgtec.com> Cc: Jia Liu <proljc@gmail.com> Cc: Alexander Graf <agraf@suse.de> Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Guan Xuetao <gxt@mprc.pku.edu.cn> Cc: Max Filippov <jcmvbkbc@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Luiz Capitulino <lcapitulino@redhat.com> Signed-off-by: Markus Armbruster <armbru@redhat.com>
* migration: Use normal VMStateDescriptions for SubsectionsJuan Quintela2015-06-121-38/+24
| | | | | | | | | | | | | | | | We create optional sections with this patch. But we already have optional subsections. Instead of having two mechanism that do the same, we can just generalize it. For subsections we just change: - Add a needed function to VMStateDescription - Remove VMStateSubsection (after removal of the needed function it is just a VMStateDescription) - Adjust the whole tree, moving the needed function to the corresponding VMStateDescription Signed-off-by: Juan Quintela <quintela@redhat.com>
* Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' ↵Peter Maydell2015-06-042-0/+22
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into staging Patch queue for ppc - 2015-06-03 Highlights this time around: - sPAPR: endian fixes, speedups, bug fixes, hotplug basics - add default ram size capability for machines (sPAPR defaults to 512MB now) # gpg: Signature made Wed Jun 3 22:59:09 2015 BST using RSA key ID 03FEDC60 # gpg: Good signature from "Alexander Graf <agraf@suse.de>" # gpg: aka "Alexander Graf <alex@csgraf.de>" * remotes/agraf/tags/signed-ppc-for-upstream: (40 commits) softmmu: support up to 12 MMU modes tcg: add TCG_TARGET_TLB_DISPLACEMENT_BITS tci: do not use CPUArchState in tcg-target.h Add David Gibson for sPAPR in MAINTAINERS file pseries: Enable in-kernel H_LOGICAL_CI_{LOAD, STORE} implementations spapr: override default ram size to 512MB machine: add default_ram_size to machine class spapr_pci: emit hotplug add/remove events during hotplug spapr_pci: enable basic hotplug operations pci: make pci_bar useable outside pci.c spapr_pci: create DRConnectors for each PCI slot during PHB realize spapr_pci: add dynamic-reconfiguration option for spapr-pci-host-bridge spapr_drc: add spapr_drc_populate_dt() spapr_events: event-scan RTAS interface spapr_events: re-use EPOW event infrastructure for hotplug events spapr_rtas: add ibm, configure-connector RTAS interface spapr: add rtas_st_buffer_direct() helper spapr_rtas: add get-sensor-state RTAS interface spapr_rtas: add set-indicator RTAS interface spapr_rtas: add get/set-power-level RTAS interfaces ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * pseries: Enable in-kernel H_LOGICAL_CI_{LOAD, STORE} implementationsDavid Gibson2015-06-032-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | qemu currently implements the hypercalls H_LOGICAL_CI_LOAD and H_LOGICAL_CI_STORE as PAPR extensions. These are used by the SLOF firmware for IO, because performing cache inhibited MMIO accesses with the MMU off (real mode) is very awkward on POWER. This approach breaks when SLOF needs to access IO devices implemented within KVM instead of in qemu. The simplest example would be virtio-blk using an iothread, because the iothread / dataplane mechanism relies on an in-kernel implementation of the virtio queue notification MMIO. To fix this, an in-kernel implementation of these hypercalls has been made, (kernel commit 99342cf "kvmppc: Implement H_LOGICAL_CI_{LOAD,STORE} in KVM" however, the hypercalls still need to be enabled from qemu. This performs the necessary calls to do so. It would be nice to provide some warning if we encounter a problematic device with a kernel which doesn't support the new calls. Unfortunately, I can't see a way to detect this case which won't either warn in far too many cases that will probably work, or which is horribly invasive. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Thomas Huth <thuth@redhat.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* | kvm: introduce kvm_arch_msi_data_to_gsiEric Auger2015-06-021-0/+5
|/ | | | | | | | | | | On ARM the MSI data corresponds to the shared peripheral interrupt (SPI) ID. This latter equals to the SPI index + 32. to retrieve the SPI index, matching the gsi, an architecture specific function is introduced. Signed-off-by: Eric Auger <eric.auger@linaro.org> Acked-by: Christoffer Dall <christoffer.dall@linaro.org> Acked-by: Cornelia Huck <cornelia.huck@de.ibm.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* kvm: add support for memory transaction attributesPaolo Bonzini2015-04-301-1/+3
| | | | | | | Let kvm_arch_post_run convert fields in the kvm_run struct to MemTxAttrs. These are then passed to address_space_rw. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Convert (ffs(val) - 1) to ctz32(val)Stefan Hajnoczi2015-04-281-2/+2
| | | | | | | | | | | | | | | | | | | This commit was generated mechanically by coccinelle from the following semantic patch: @@ expression val; @@ - (ffs(val) - 1) + ctz32(val) The call sites have been audited to ensure the ffs(0) - 1 == -1 case never occurs (due to input validation, asserts, etc). Therefore we don't need to worry about the fact that ctz32(0) == 32. Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> Message-id: 1427124571-28598-5-git-send-email-stefanha@redhat.com Signed-off-by: Kevin Wolf <kwolf@redhat.com>
* target-ppc: don't invalidate msr MSR_HVB bit in cpu_post_loadMark Cave-Ayland2015-04-171-2/+2
| | | | | | | | | | | | | | | | | The invalidation code introduced in commit 2360b works by inverting most bits of env->msr to ensure that hreg_store_msr() will forcibly update the CPU env state to reflect the new msr value post-migration. Unfortunately hreg_store_msr() is called with alter_hv set to 0 which preserves the MSR_HVB state from the CPU env which is now the opposite value to what it should be. Ensure that we don't invalidate the msr MSR_HVB bit during cpu_post_load so that the correct value is restored. This fixes suspend/resume for PPC64. Reported-by: Stefan Berger <stefanb@linux.vnet.ibm.com> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Alexander Graf <agraf@suse.de> Message-id: 1429255009-12751-1-git-send-email-mark.cave-ayland@ilande.co.uk Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-ppc: Remove POWER5+ v0.0 that never existedAlexey Kardashevskiy2015-03-252-5/+2
| | | | | | | | | | | | | | | | IBM uses low 16bits to specify the chip version of a POWER CPU. So there has never been an actual silicon with PVR = 0x003B0000. The first silicon would have PVR 0x003B0100 but it is very unlikely to find it in any machine shipped to any customer as it was too raw. This removes CPU_POWERPC_POWER5P_v00 definition and changes POWER5+ and POWERgs aliases (which are synonyms) to point to POWER5+_v2.1 which can still be found in real machines. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Andreas Färber <afaerber@suse.de> [agraf: fix commit message] Signed-off-by: Alexander Graf <agraf@suse.de>
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