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* target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift InstructionsTom Musta2014-03-053-0/+16
| | | | | | | | | | | | | This patch adds the vector doublword rotate and shift instructions introduced in Power ISA Version 2.07: - Vector Rotate Left Doubleword instruction (vrld) - Vector Shift Left Doubleword (vsld) - Vector Shift Right Doubleword (vsrd) - Vector Shift Right Algegbraic Doubleword (vsrad) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Change Bit Masks to Support 64-bit Rotates and ShiftsTom Musta2014-03-051-25/+15
| | | | | | | | | | | | | | | | | | | | | | | | Existing code in the VROTATE, VSL and VSR macros for the Altivec rotate and shift helpers uses a formula to compute a bit mask used to extract the rotate/shift amount from the VRB register. What is desired is: mask = (1 << (3 + log2(sizeof(element)))) - 1 but what is implemented is: mask = (1 << (3 + (sizeof(element)/2))) - 1 This produces correct answers when "element" is uint8_t, uint16_t or uint_32t. But it breaks down when element is uint64_t. This patch corrects the situation. Since the mask is known at compile time, the macros are changed to simply accept the mask as an argument. Subsequent patches in this series will add double-word variants of rotates and shifts and thus take advantage of this fix. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Vector Merge InstructionsTom Musta2014-03-051-0/+37
| | | | | | | | | This patch adds the Vector Merge Even Word (vmrgew) and Vector Merge Odd Word (vmrgow) instructions introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Unpack Signed Word InstructionsTom Musta2014-03-053-0/+8
| | | | | | | | | | | This patch adds the Unpack Signed Word instructions introduced in Power ISA Version 2.07: - Vector Unpack High Signed Word (vupkusw) - Vector Unpack Low Signed Word (vupklsw) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Pack Doubleword InstructionsTom Musta2014-03-053-0/+16
| | | | | | | | | | | | | This patch adds the Vector Pack Doubleword instructions introduced in Power ISA Version 2.07: - Vector Pack Signed Doubleword Signed Saturate (vpksdss) - Vector Pack Signed Doubleword Unsigned Saturate (vpksdus) - Vector Pack Unsigned Doubleword Unsigned Modulo (vpkudum) - Vector Pack Unsigned Doubleword Unsigned Saturate (vpkudus) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Vector Min/Max Doubleword InstructionsTom Musta2014-03-053-0/+14
| | | | | | | | This patch adds the Vector Minimum and Maximum Doubleword instructions that are introduced in Power ISA Version 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Vector Population Count InstructionsTom Musta2014-03-053-4/+36
| | | | | | | | This patch adds the Vector Population Count instructions introduced in Power ISA Version 2.07: vpopcntb, vpopcnth, vpopcntw and vpopcntd. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Add Vector Count Leading ZeroesTom Musta2014-03-053-0/+43
| | | | | | | | This patch adds the Vector Count Leading Zeroes instructions introduced in Power ISA Version 2.07 - vclzb, vclzh, vclzw and vclzd. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: vmuluw InstructionTom Musta2014-03-053-1/+6
| | | | | | | | | | | | | | This patch adds the Vector Multiply Unsigned Word Modulo (vmuluwm) instruction. The existing VARITH_DO macro is re-used to (trivially) instantiate the helper code. Since bits 21-31 of any vmuluwm instruction is 137, the instruction is coded as a dual to vmulouw (bits 21-31 = 136). Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Multiply Even/Odd Word InstructionsTom Musta2014-03-053-0/+14
| | | | | | | | | | | | | This patch adds the Multilpy Even/Odd Word instructions that are introduced in Power ISA Version 2.07: - Vector Multiply Even Unsigned Word (vmuleuw) - Vector Multiply Even Signed Word (vmulesw) - Vector Multiply Odd Unsigned Word (vmulouw) - Vector Multiply Odd Signed Word (vmulosw) Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Change VMUL_DO to Support 64-bit IntegersTom Musta2014-03-051-12/+14
| | | | | | | | | | | | | | | | | | This VMUL_DO macro provides support for the various vmule* and vmulo* instructions. These instructions multiply vector elements, producing products that are one size larger; e.g. vmuleub multiplies unsigned 8-bit elements and produces a 16 bit unsigned element. The existing macro works correctly for the existing instructions (8-bit, and 16-bit source elements) but does not work correctly for 32-bit source elements. This patch adds an explicit cast to the multiplicands, forcing them to be of the target element type. This is required for the forthcoming patches that add the vmul[eo][us]w instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword ModuloTom Musta2014-03-053-0/+7
| | | | | | | | | | | This patch adds two Altivec unsigned doublword modulo instructions that are introduced in Power ISA Version V2.07: - vaddudm : Vector Add Unsigned Doubleword Modulo - vsubudm : Vector Subtrace Unsigned Doubleword Modulo Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Vector Logical InstructionsTom Musta2014-03-051-0/+11
| | | | | | | | This patch adds the Vector Logical Instructions that are introduced in Power ISA Version 2.07: veqv, vnand and vorc. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Add Support for R-Form Dual InstructionsTom Musta2014-03-051-0/+35
| | | | | | | | | | | | | | | | | Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31 (aka the "Rc" bit) as an opcode but also use bit 21 as an actual Rc bit. QEMU for PowerPC typically uses bits 0-5 and 21-30 for opcodes. This patch introduces a generator macro that injects an auxiliary handler which decodes both bits 21 and 31 and invokes one of four standard handlers. Since the instructions are not, in general, from the same version of the ISA, two sets of PPC_*/PPC2_* flags are supported. This patch also introduces a macro to insert two entries into the opcode table -- one for bit 21 equal to 0 and one for bit 21 equal to 1. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Add Opcode Macro for VX Form InstructionsTom Musta2014-03-051-0/+5
| | | | | | | | | | This patch adds a macro to insert an entry into the opcode table for Altivec Power ISA Version 2.07 instructions. The macro is similar to the GEN_VXFORM macro except that it tags the entry with the PPC2_ALTIVEC_207 flag rather than PPC_ALTIVEC. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Add Support for Dual Altivec InstructionsTom Musta2014-03-051-0/+24
| | | | | | | | | | | | | | Some Alitvec instructions introduced in Power ISA Version 2.07 use bit 31 (aka the "Rc" bit) as an opcode bit. However, QEMU for PowerPC uses bits 0-5 and 21-30 for opcodes and not bit 31. This patch introduces macros that will handle this situation by injecting an auxiliary handler which decodes bit 31 in invokes one of two standard handlers. Since the instructions are not, in general, from the same version of the ISA, two sets of PPC_*/PPC2_* instruction tags are supported. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Add GEN_VXFORM3Tom Musta2014-03-051-0/+19
| | | | | | | | This patch adds generator macro for Altivec instructions that have 3 source AVR operands. The macro is similar to the 2 operand form. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Update AVR StructureTom Musta2014-03-051-0/+4
| | | | | | | | | This patch updates the ppc_avr_t data structure to include elements for signed 64-bit integers and (conditionally) unsigned 128 bit integers. These elements will be in instructions models later on in this patch series. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Altivec 2.07: Add Instruction FlagTom Musta2014-03-052-2/+5
| | | | | | | | | | This patch adds a flag that will be used to tag the Altivec instructions introduced in Power ISA Version 2.07. The flag is added to Power8 model since P8 supports these instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add Store Quadword ConditionalTom Musta2014-03-051-0/+21
| | | | | | | | | This patch adds the Store Quadword Conditionl (stqcx.) instruction which is introduced in Power ISA 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> [agraf: fix compile error when !TARGET_PPC64] Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add Load Quadword and ReserveTom Musta2014-03-052-0/+38
| | | | | | | | This patch adds the Load Quadword and Reserve (lqarx) instruction, which is new in Power ISA 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Store QuadwordTom Musta2014-03-051-16/+23
| | | | | | | | | This patch adds support for the Store Quadword instruction in user mode. Prior to Power ISA 2.07, stq was legal only in privileged mode. Support for Little Endian mode is also new in ISA 2.07. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Load QuadwordTom Musta2014-03-052-15/+23
| | | | | | | | | | | | | | This patch adds the Book I (user space) Load Quadword (lq) instruction. This instruction was introduced into Book I in Power ISA V2.07. Previous versions of the architecture supported this as a privileged instruction. Previous versions of the architecture also did not support Little Endian mode. Note that this patch also adds the PPC_64BX flag to the Power8 model, which enables the lq instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add is_user_mode Utility RoutineTom Musta2014-03-051-0/+14
| | | | | | | | | This patch adds a boolean function is_user_mode that can be re-used in translation code that is sensitive to the MSR[PR] (user-mode) state. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add Flag for ISA 2.07 Load/Store Quadword InstructionsTom Musta2014-03-052-2/+5
| | | | | | | | | | | This patch adds a flag to identify the load/store quadword instructions that are introduced with Power ISA 2.07. The flag is added to the Power8 model since P8 supports these instructions. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add bctar InstructionTom Musta2014-03-051-1/+10
| | | | | | | | This patch adds the Branch Conditional to Address Register (bctar) instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add Target Address SPR (TAR) to Power8Tom Musta2014-03-052-1/+14
| | | | | | | | | | | | | This patch adds support for the Target Address Register (TAR) to the Power8 model. Because supported SPRs are typically identified in an init_proc_*() function and because the Power8 model is currently just using the init_proc_POWER7() function, a new init_proc_POWER8() function is added and plugged into the P8 model. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add Flag for bctarTom Musta2014-03-052-3/+5
| | | | | | | | | | | This patch adds a flag for the bctar instruction. This instruction is being introduced via Power ISA 2.07. Also, the flag is added to the Power8 machine model since the P8 processor supports this instruction. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Fix xxpermdi When T==A or T==BTom Musta2014-03-051-8/+33
| | | | | | | | | | The existing implementation of xxpermdi is defective if the target VSR is also a source VSR. This patch fixes the defect in this case but also preserves the simpler, two TCG operation implementation when the target is not once of the two sources. Signed-off-by: Tom Musta <tommusta@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: add extended opcodes for dcbt/dcbtstCédric Le Goater2014-03-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | The latest glibc provides a memrchr routine using an extended opcode of the 'dcbt' instruction : 00000000000a7cc0 <memrchr>: a7cc0: 11 00 4c 3c addis r2,r12,17 a7cc4: b8 f8 42 38 addi r2,r2,-1864 a7cc8: 14 2a e3 7c add r7,r3,r5 a7ccc: d0 00 07 7c neg r0,r7 a7cd0: ff ff e7 38 addi r7,r7,-1 a7cd4: 78 1b 6a 7c mr r10,r3 a7cd8: 24 06 e6 78 rldicr r6,r7,0,56 a7cdc: 60 00 20 39 li r9,96 a7ce0: 2c 32 09 7e dcbtt r9,r6 .... which breaks grep, and other commands, in TCG mode : invalid bits: 02000000 for opcode: 1f - 16 - 08 (7e09322c) 00003fff799feca0 This patch adds the extended opcodes for dcbt/dcbtst as no-ops just like the 'dcbt' instruction. Signed-off-by: Cédric Le Goater <clg@fr.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: KVM: suppress warnings about not supported SPRsAlexey Kardashevskiy2014-03-051-4/+3
| | | | | | | | PR KVM lacks support of many SPRs in set/get one register API but it does really break PR KVM. So convert them to switchable traces for now. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: KVM: store SLB slot numberAlexey Kardashevskiy2014-03-051-0/+3
| | | | | | | | | | | | | | | | When ppc_store_slb() is called from kvm_arch_get_registers(), it stores a SLB in CPUPPCState::slb[slot]. However it drops the slot number from ESID so when kvm_arch_put_registers() puts SLBs back to KVM, they do not have correct "index" field anymore. This broke migration with LPCR_AIR enabled as now the guest is handling interrupts in virtual mode and unable to reconstruct correct SLBs anymore. This adds "index" field for valid SLBs when putting them to KVM. Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru> Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Cc: qemu-stable@nongnu.org Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add ISA2.06 lfiwzx InstructionTom Musta2014-03-051-0/+15
| | | | | | | | | | This patch adds the Load Floating Point as Integer Word and Zero Indexed (lfiwzx) instruction which was introduced in Power ISA 2.06. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Enable frsqrtes on Power7 and Power8Tom Musta2014-03-051-0/+3
| | | | | | | | | | | | The frsqrtes instruction was introduced prior to ISA 2.06 and is support on both the Power7 and Power8 processors. However, this instruction is handled as illegal in the current QEMU emulation machines. This patch enables the existing implemention of frsqrtes in the P7 and P8 machines. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add ISA 2.06 ftsqrtTom Musta2014-03-053-0/+42
| | | | | | | | | This patch adds the Floating Point Test for Square Root instruction which was introduced in Power ISA 2.06. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add ISA 2.06 ftdiv InstructionTom Musta2014-03-053-10/+61
| | | | | | | | | This patch adds the Floating Point Test for Divide instruction which was introduced in Power ISA 2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add Flag for Power ISA V2.06 Floating Point Test InstructionsTom Musta2014-03-052-4/+9
| | | | | | | | | This patch adds a flag for Floating Point Test instructions that were introduced in Power ISA V2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Fix and enable fri[mnpz]Tom Musta2014-03-052-7/+14
| | | | | | | | | | | | | | The fri* series of instructions was introduced prior to ISA 2.06 and is supported on Power7 and Power8 hardware. However, the instruction is still considered illegal in the P7 and P8 QEMU emulation models. This patch enables these instructions for the P7 and P8 machines. Also, the existing helper is modified to correctly handle some of the boundary cases (NaNs and the inexact flag). Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add ISA 2.06 fcfid[u][s] InstructionsTom Musta2014-03-053-9/+31
| | | | | | | | | | | This patch adds the fcfids, fcfidu and fcfidus instructions which were introduced in Power ISA 2.06B. A common macro is provided to eliminate repetitious code, and the existing fcfid instruction is refactored to use this macro. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add ISA2.06 Float to Integer InstructionsTom Musta2014-03-053-87/+49
| | | | | | | | | | | | | | | | | | | This patch adds the four floating point to integer conversion instructions introduced by Power ISA V2.06: - Floating Convert to Integer Word Unsigned (fctiwu) - Floating Convert to Integer Word Unsigned with Round Toward Zero (fctiwuz) - Floating Convert to Integer Doubleword Unsigned (fctidu) - Floating Convert to Integer Doubleword Unsigned with Round Toward Zero (fctiduz) A common macro is developed to eliminate repetitious code. Existing instructions are also refactoried to use this macro (fctiw, fctiwz, fctid, fctidz). Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add Flag for ISA V2.06 Floating Point ConversionTom Musta2014-03-052-4/+7
| | | | | | | | | This patch adds a flag for the floating point conversion instructions introduced in Power ISA 2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add ISA 2.06 stbcx. and sthcx. InstructionsTom Musta2014-03-051-47/+44
| | | | | | | | | | This patch adds the byte and halfword variants of the Store Conditional instructions. A common macro is introduced and the existing implementations of stwcx. and stdcx. are refactored to use this macro. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add ISA2.06 lbarx, lharx InstructionsTom Musta2014-03-051-26/+24
| | | | | | | | | | | | This patch adds the byte and halfword variants of the Load and Reserve instructions. Since there is much commonality among all forms of Load and Reserve, a macro is provided and the existing implementations of lwarx and ldarx are refactoried to use this macro. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add Flag for ISA2.06 Atomic InstructionsTom Musta2014-03-052-4/+10
| | | | | | | | | This patch adds a flag for the atomic instructions introduced in Power ISA V2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add ISA 2.06 divwe[o] InstructionsTom Musta2014-03-053-0/+37
| | | | | | | | | This patch addes the signed Divide Word Extended instructions which were introduced in Power ISA 2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add ISA 2.06 divweu[o] InstructionsTom Musta2014-03-053-0/+37
| | | | | | | | | This patch addes the Unsigned Divide Word Extended instructions which were introduced in Power ISA 2.06B. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add ISA2.06 divde[o] InstructionsTom Musta2014-03-053-1/+28
| | | | | | | | | | This patch adds the Divide Doubleword Extended instructions. The implementation builds on the unsigned helper provided in the previous patch. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add ISA2.06 divdeu[o] InstructionsTom Musta2014-03-053-0/+49
| | | | | | | | | | | | | This patch adds the Divide Doubleword Extended Unsigned instructions. This instruction requires dividing a 128-bit value by a 64 bit value. Since 128 bit integer division is not supported in TCG, a helper is used. An architecture independent 128-bit division routine is added to host-utils. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> [agraf: use ||] Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add Flag for ISA2.06 Divide Extended InstructionsTom Musta2014-03-052-4/+7
| | | | | | | | | | This patch adds a flag for the Divide Extended instructions that were introduced in Power ISA V2.06B. The flag is added to the Power7 and Power8 models. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Add ISA2.06 bpermd InstructionTom Musta2014-03-055-5/+41
| | | | | | | | | | This patch adds the Bit Permute Doubleword (bpermd) instruction, which was introduced in Power ISA 2.06 as part of the base 64-bit architecture. Signed-off-by: Tom Musta <tommusta@gmail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Alexander Graf <agraf@suse.de>
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