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* ppc: remove unused variablesBlue Swirl2012-02-111-3/+0
| | | | | | | | | Fix this error: /src/qemu/target-ppc/helper.c: In function 'booke206_tlb_to_page_size': /src/qemu/target-ppc/helper.c:1296:14: error: variable 'tlbncfg' set but not used [-Werror=unused-but-set-variable] Tested-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* PPC: E500: Populate L1CFG0 SPRAlexander Graf2012-02-021-1/+4
| | | | | | | | | | | | When running Linux on e500 with powersave-nap enabled, Linux tries to read out the L1CFG0 register and calculates some things from it. Passing 0 there ends up in a division by 0, resulting in -1, resulting in badness. So let's populate the L1CFG0 register with reasonable defaults. That way guests aren't completely confused. Reported-by: Shrijeet Mukherjee <shm@cumulusnetworks.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: e500mc: Enable processor controlAlexander Graf2012-02-021-1/+1
| | | | | | | | The e500mc implements Embedded.Processor Control, so enable it and thus enable guests to IPI each other. This makes -smp work with -cpu e500mc. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: E500: Implement msgsndAlexander Graf2012-02-023-0/+35
| | | | | | | | This patch implements the msgsnd instruction. It is part of the Embedded.Processor Control specification and allows one CPU to IPI another CPU without going through an interrupt controller. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: E500: Implement msgclrAlexander Graf2012-02-023-0/+54
| | | | | | | | This patch implements the msgclr instruction. It is part of the Embedded.Processor Control specification and clears pending doorbell interrupts on the current CPU. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Enable doorbell excp handlersAlexander Graf2012-02-021-14/+2
| | | | | | | | | We already had all the code available to have doorbell exceptions be handled properly. It was just disabled. Enable it, so we can rely on it. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Add CPU feature for processor controlAlexander Graf2012-02-021-1/+3
| | | | | | | We're soon going to implement processor control features. Add the feature flag, so we're well prepared. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: E500: Add doorbell definesAlexander Graf2012-02-021-0/+16
| | | | | | | | We're going to introduce doorbell instructions (called processor control in the spec) soon. Add some defines for easier patch readability later. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: E500: Add some more excp vectorsAlexander Graf2012-02-021-1/+4
| | | | | | | Our EXCP list is getting outdated. By now, 3 new exception vectors have been introduced. Update the list so we have everything at one place. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: booke206: move avail check to tlbweAlexander Graf2012-02-022-7/+10
| | | | | | | | | | | | We can have TLBs that only support a single page size. This is defined by the absence of the AVAIL flag in TLBnCFG. If this is the case, we currently write invalid size info into the TLB, but override it on internal fault. Let's move the check over to tlbwe, so we don't have the AVAIL check in the hotter fault path. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: booke206: Check for TLB overrunAlexander Graf2012-02-024-1/+29
| | | | | | | | Our internal helpers to fetch TLB entries were not able to tell us that an entry doesn't even exist. Pass an error out if we hit such a case to not accidently pass beyond the TLB array. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: booke206: Implement tlbilxAlexander Graf2012-02-023-0/+102
| | | | | | | | | | | The PowerPC 2.06 BookE ISA defines an opcode called "tlbilx" which is used to flush TLB entries. It's the recommended way of flushing in virtualized environments. So far we got away without implementing it, but Linux for e500mc uses this instruction, so we better add it :). Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: booke206: Check for min/max TLB entry sizeAlexander Graf2012-02-021-0/+11
| | | | | | | | | When setting a TLB entry, we need to check if the TLB we're putting it in actually supports the given size. According to the 2.06 PowerPC ISA, a value that's out of range can either be redefined to something implementation dependent or we can raise an illegal opcode exception. We do the latter. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: booke: add tlbnps handlingAlexander Graf2012-02-021-0/+25
| | | | | | | | | | When using MAV 2.0 TLB registers, we have another range of TLB registers available to read the supported page sizes from. Add SPR definitions for those and add a helper function that we can use to receive such a bitmap even when using MAV 1.0. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: booke206: allow NULL raddr in ppcmas_tlb_checkAlexander Graf2012-02-021-1/+4
| | | | | | | | We might want to call the tlb check function without actually caring about the real address resolution. Check if we really should write the value back. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: rename msync to msync_4xxAlexander Graf2012-02-021-2/+2
| | | | | | | | | The msync instruction as defined today is only valid on 4xx cores, not on e500 which also supports msync, but treats it the same way as sync. Rename it to reflect that it's 4xx only. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: e500: msync is 440 only, e500 has real syncAlexander Graf2012-02-022-5/+4
| | | | | | | | The e500 CPUs don't use 440's msync which falls on the same opcode IDs, but instead use the real powerpc sync instruction. This is important, since the invalid mask differs between the two. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: e500mc: add missing IVORs to bitmapAlexander Graf2012-02-021-1/+5
| | | | | | | E500mc supports IVORs 36-41. Add them to the support mask. Drop SPE support too. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Add IVOR 38-42Alexander Graf2012-02-022-14/+20
| | | | | | | | Our code only knows IVORs up to 37. Add the new ones defined in ISA 2.06 from 38 - 42. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Andreas Färber <afaerber@suse.de>
* PPC: KVM: Update HIOR code to new interfaceAlexander Graf2012-02-021-3/+7
| | | | | | | | | | | | | | | | | | Unfortunately the HIOR setting code slipped into upstream QEMU before it was pulled into upstream KVM. And since Murphy is always right, comments on the patches only emerged on the pull request leading to changes in the interface. So here's an update to the HIOR setting. While at it, I also relaxed it a bit since for HV KVM we can already run fine without and 3.2 works just fine with HV KVM but when not setting HIOR. We will only need this when running PAPR in PR KVM. Since we accidently changed the ABI and API along the way, we have to update the underlying kernel headers together with the code that uses it to not break bisectability. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Enable 440EP CPU targetAlexander Graf2012-01-211-11/+5
| | | | | | | Now that we have 440 TLB emulation, we can also support running the 440EP CPU target in system emulation mode. Signed-off-by: Alexander Graf <agraf@suse.de>
* kvm: fix build error in ppc kvm due to memory_region_init_ram_ptr() changeAvi Kivity2012-01-081-1/+2
| | | | | | | | Commit c5705a772 ("vmstate, memory: decouple vmstate from memory API") changed the signature of memory_region_init_ram_ptr() but did not update a caller in the ppc kvm module. Fix. Signed-off-by: Avi Kivity <avi@redhat.com>
* PPC: Add description for the Freescale e500mc core.Varun Sethi2012-01-031-6/+50
| | | | | | | | | | | | | This core is found on chips such as p4080, p3041, p2040, and p5020. More needs to be done to make this viable for TCG (such as missing SPRs and instructions), but this suffices to get KVM running with appropriate kernel support. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> [scottwood@freescale.com: tweak some flags] Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* kvm-ppc: halt secondary cpus when guest resetLiu Yu-B132012012-01-031-1/+1
| | | | | | | | | When guest reset, we need to halt secondary cpus until guest kick them. This already works for tcg. The patch add the support for kvm. Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de> [agraf: remove in-kernel irqchip code]
* PPC: monitor: add ability to dump SLB entriesNishanth Aravamudan2012-01-031-0/+28
| | | | | | | | | | | | When run with a PPC Book3S (server) CPU Currently 'info tlb' in the qemu monitor reports "dump_mmu: unimplemented". However, during bringup work, it can be quite handy to have the SLB entries, which are available in the CPUPPCState. This patch adds an implementation of info tlb for book3s, which dumps the SLB. Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* fix spelling in target sub directoryDong Xu Wang2011-12-023-5/+5
| | | | | | | | | | | Cc: Richard Henderson <rth@twiddle.net> Cc: Edgar E. Iglesias <edgar.iglesias@gmail.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Alexander Graf <agraf@suse.de> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Dong Xu Wang <wdongxu@linux.vnet.ibm.com> Signed-off-by: Stefan Hajnoczi <stefanha@linux.vnet.ibm.com>
* PPC: Fix for the gdb single step problem on an rfi instructionSebastian Bauer2011-11-111-1/+3
| | | | | | | | | | | | | | | When using gdb to single step a ppc interrupt routine, the execution flow passes the rfi instruction without actually returning from the interrupt. The patch fixes this by avoiding to update the nip when the debug exception is raised and a previous POWERPC_EXCP_SYNC was set. The latter is the case only, if code for rfi or a related instruction was generated. Signed-off-by: Sebastian Bauer <mail@sebastianbauer.info> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriateDavid Gibson2011-10-312-3/+43
| | | | | | | | | | | | | | | | | | | The CPU state contains two bitmaps, initialized from the CPU spec which describes which instructions are implemented on the CPU. A couple of bits are defined which cover instructions (VSX and DFP) which are not currently implemented in TCG. So far, these are only used to handle the case of -cpu host because a KVM guest can use the instructions when the host CPU supports them. However, it's a mild layering violation to simply not include those bits in the CPU descriptions for those CPUs that do support them, just because we can't handle them in TCG. This patch corrects the situation, so that the instruction bits _are_ shown correctly in the cpu spec table, but are masked out from the cpu state in the non-KVM case. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* pseries: Allow writes to KVM accelerated TCE tableDavid Gibson2011-10-301-1/+1
| | | | | | | | | | | | | | | | | | | | Sufficiently recent kernels include a KVM call to accelerate use of PAPR TCE tables (IOMMU), which are used by PAPR virtual IO devices. This involves qemu mapping the TCE table in from a kernel obtained fd, which currently we do with PROT_READ only. This is a hangover from early (never released) versions of this kernel interface which only permitted read-only mappings and required us to destroy and recreate the table when we needed to clear it from qemu. Now, the kernel permits read-write mappings, and we rely on this to clear the table in spapr_vio_quiesce_one(). However, due to insufficient testing, I forgot to update the actual mapping of the table in kvmppc_create_spapr_tce() to add PROT_WRITE to the mmap(). This patch corrects the oversight. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* KVM: PPC: Override host vmx/vsx/dfp only when information knownAlexander Graf2011-10-301-3/+9
| | | | | | | | | | | | | | | | The -cpu host feature tries to find out the host capabilities based on device tree information. However, we don't always have that available because it's an optional property in dt. So instead of force unsetting values depending on an unreliable source of information, let's just try to be clever about it and not override capabilities when we don't know the device tree pieces. This fixes altivec with -cpu host on YDL PowerStations. Reported-by: Nishanth Aravamudan <nacc@us.ibm.com> Acked-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Fix up usermode only buildsDavid Gibson2011-10-301-0/+4
| | | | | | | | The recent usage of MemoryRegion in kvm_ppc.h breaks builds with CONFIG_USER_ONLY=y. This patch fixes it. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* pseries: Correct vmx/dfp handling in both KVM and TCG casesDavid Gibson2011-10-303-17/+44
| | | | | | | | | | | | | | | | | | | | Currently, when KVM is enabled, the pseries machine checks if the host CPU supports VMX, VSX and/or DFP instructions and advertises accordingly in the guest device tree. It does this regardless of what CPU is selected on the command line. On the other hand, when in TCG mode, it never advertises any of these facilities, even basic VMX (Altivec) which is supported in TCG. Now that we have a -cpu host option for ppc, it is fairly straightforward to fix both problems. This patch changes the -cpu host code to override the basic cpu spec derived from the PVR with information queried from the host avout VMX, VSX and DFP capability. The pseries code then uses the instruction availability advertised in the cpu state to set the guest device tree correctly for both the KVM and TCG cases. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Disable non-440 CPUs for ppcemb targetAlexander Graf2011-10-301-0/+24
| | | | | | | | | | | | The sole reason we have the ppcemb target is to support MMUs that have less than the usual 4k possible page size. There are very few of these chips and I don't want to add additional QA and testing burden to everyone to ensure that code still works when TARGET_PAGE_SIZE is not 4k. So this patch disables all CPUs except for MMU_BOOKE capable ones from the ppcemb target. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Bump qemu-system-ppc to 64-bit physical address spaceAlexander Graf2011-10-301-1/+1
| | | | | | | Some 32-bit PPC CPUs can use up to 36 bit of physical address space. Treat them accordingly in the qemu-system-ppc binary type. Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Add cpu defs for POWER7 revisions 2.1 and 2.3David Gibson2011-10-301-0/+4
| | | | | | | | This patch adds cpu specs to the table for POWER7 revisions 2.1 and 2.3. This allows -cpu host to be used on these host cpus. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: First cut implementation of -cpu hostDavid Gibson2011-10-304-1/+33
| | | | | | | | | | | | | | | | | | | | | For convenience with kvm, x86 allows the user to specify -cpu host on the qemu command line, which means make the guest cpu the same as the host cpu. This patch implements the same option for ppc targets. For now, this just read the host PVR (Processor Version Register) and selects one of our existing CPU specs based on it. This means that the option will not work if the host cpu is not supported by TCG, even if that wouldn't matter for use under kvm. In future, we can extend this in future to override parts of the cpu spec based on information obtained from the host (via /proc/cpuinfo, the host device tree, or explicit KVM calls). That will let us handle cases where the real kvm-virtualized CPU doesn't behave exactly like the TCG-emulated CPU. With appropriate annotation of the CPU specs we'll also then be able to use host cpus under kvm even when there isn't a matching full TCG model. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Remove broken partial PVR matchingDavid Gibson2011-10-301-30/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ppc target contains a ppc_find_by_pvr() function, which looks up a CPU spec based on a PVR (that is, based on the value in the target cpu's Processor Version Register). PVR values contain information on both the cpu model (upper 16 bits, usually) and on the precise revision (low 16 bits, usually). ppc_find_by_pvr, as well as making exact PVR matches, attempts to find "close" PVR matches, when we don't have a CPU spec for the exact revision specified. This sounds like a good idea, execpt that the current logic is completely nonsensical. It seems to assume CPU families are subdivided bit by bit in the PVR in a way they just aren't. Specifically, it requires a match on all bits of the specified pvr up to the last non-zero bit. This has the bizarre effect that when the low bits are simply a sequential revision number (a common though not universal pattern), then odd specified revisions must be matched exactly, whereas even specified revisions will also match the next odd revision, likewise for powers of 4, 8 and so forth. To correctly do inexact matching we'd need to re-organize the table of CPU specs to include a mask showing what PVR range the spec is compatible with (similar to the cputable code in the Linux kernel). For now, just remove the bogosity by only permitting exact PVR matches. That at least makes the matching simple and consistent. If we need inexact matching we can add the necessary per-subfamily masks later. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* pseries: Add device tree properties for VMX/VSX and DFP under kvmDavid Gibson2011-10-302-0/+22
| | | | | | | | | | | | | | | | | | | | | Sufficiently recent PAPR specifications define properties "ibm,vmx" and "ibm,dfp" on the CPU node which advertise whether the VMX vector extensions (or the later VSX version) and/or the Decimal Floating Point operations from IBM's recent POWER CPUs are available. Currently we do not put these in the guest device tree and the guest kernel will consequently assume they are not available. This is good, because they are not supported under TCG. VMX is similar enough to Altivec that it might be trivial to support, but VSX and DFP would both require significant work to support in TCG. However, when running under kvm on a host which supports these instructions, there's no reason not to let the guest use them. This patch, therefore, checks for the relevant support on the host CPU and, if present, advertises them to the guest as well. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Generalize the kvmppc_get_clockfreq() functionDavid Gibson2011-10-301-11/+24
| | | | | | | | | | | | | | | Currently the kvmppc_get_clockfreq() function reads the host's clock frequency from /proc/device-tree, which is useful to past to the guest in KVM setups. However, there are some other host properties advertised in the device tree which can also be relevant to the guests. This patch, therefore, replaces kvmppc_get_clockfreq() which can retrieve any named, single integer property from the host device tree's CPU node. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* Set an invalid-bits mask for each SPE instructionsFabien Chouteau2011-10-301-229/+271
| | | | | | | | | | | SPE instructions are defined by pairs. Currently, the invalid-bits mask is set for the first instruction, but the second one can have a different mask. example: GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE), Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* pseries: Use Book3S-HV TCE acceleration capabilitiesDavid Gibson2011-10-302-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | The pseries machine of qemu implements the TCE mechanism used as a virtual IOMMU for the PAPR defined virtual IO devices. Because the PAPR spec only defines a small DMA address space, the guest VIO drivers need to update TCE mappings very frequently - the virtual network device is particularly bad. This means many slow exits to qemu to emulate the H_PUT_TCE hypercall. Sufficiently recent kernels allow this to be mitigated by implementing H_PUT_TCE in the host kernel. To make use of this, however, qemu needs to initialize the necessary TCE tables, and map them into itself so that the VIO device implementations can retrieve the mappings when they access guest memory (which is treated as a virtual DMA operation). This patch adds the necessary calls to use the KVM TCE acceleration. If the kernel does not support acceleration, or there is some other error creating the accelerated TCE table, then it will still fall back to full userspace TCE implementation. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* pseries: Allow KVM Book3S-HV on PPC970 CPUSDavid Gibson2011-10-302-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | At present, using the hypervisor aware Book3S-HV KVM will only work with qemu on POWER7 CPUs. PPC970 CPUs also have hypervisor capability, but they lack the VRMA feature which makes assigning guest memory easier. In order to allow KVM Book3S-HV on PPC970, we need to specially allocate the first chunk of guest memory (the "Real Mode Area" or RMA), so that it is physically contiguous. Sufficiently recent host kernels allow such contiguous RMAs to be allocated, with a kvm capability advertising whether the feature is available and/or necessary on this hardware. This patch enables qemu to use this support, thus allowing kvm acceleration of pseries qemu machines on PPC970 hardware. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de> --- agraf: fix to use memory api
* pseries: Support SMT systems for KVM Book3S-HVDavid Gibson2011-10-303-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | Alex Graf has already made qemu support KVM for the pseries machine when using the Book3S-PR KVM variant (which runs the guest in usermode, emulating supervisor operations). This code allows gets us very close to also working with KVM Book3S-HV (using the hypervisor capabilities of recent POWER CPUs). This patch moves us another step towards Book3S-HV support by correctly handling SMT (multithreaded) POWER CPUs. There are two parts to this: * Querying KVM to check SMT capability, and if present, adjusting the cpu numbers that qemu assigns to cause KVM to assign guest threads to cores in the right way (this isn't automatic, because the POWER HV support has a limitation that different threads on a single core cannot be in different guests at the same time). * Correctly informing the guest OS of the SMT thread to core mappings via the device tree. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: booke timersFabien Chouteau2011-10-062-0/+66
| | | | | | | | | | While working on the emulation of the freescale p2010 (e500v2) I realized that there's no implementation of booke's timers features. Currently mpc8544 uses ppc_emb (ppc_emb_timers_init) which is close but not exactly like booke (for example booke uses different SPR). Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* KVM: PPC: Use HIOR setting for -M pseries with PR KVMAlexander Graf2011-10-061-3/+22
| | | | | | | | | | | | When running with PR KVM, we need to set HIOR directly. Thankfully there is now a new interface to set registers individually so we can just use that and poke HIOR into the guest vcpu's HIOR register. While at it, this also sets SDR1 because -M pseries requires it to run. With this patch, -M pseries works properly with PR KVM. Signed-off-by: Alexander Graf <agraf@suse.de>
* Gdbstub: handle read of fpscrFabien Chouteau2011-10-061-2/+1
| | | | | Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* Implement POWER7's CFAR in TCGDavid Gibson2011-10-063-1/+58
| | | | | | | | | | | | | | | This patch implements support for the CFAR SPR on POWER7 (Come From Address Register), which snapshots the PC value at the time of a branch or an rfid. The latest powerpc-next kernel also catches it and can show it in xmon or in the signal frames. This works well enough to let recent kernels boot (which otherwise oops on the CFAR access). It hasn't been tested enough to be confident that the CFAR values are actually accurate, but one thing at a time. Signed-off-by: Ben Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: booke206: use MAV=2.0 TSIZE definition, fix 4G pagesScott Wood2011-10-062-4/+5
| | | | | | | | | | | This definition is backward compatible with MAV=1.0 as long as the guest does not set reserved bits in MAS1/MAS4. Also, fix the shift in booke206_tlb_to_page_size -- it's the base that should be able to hold a 4G page size, not the shift count. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: booke206: add "info tlb" supportScott Wood2011-10-062-0/+90
| | | | | Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* kvm: ppc: booke206: use MMU APIScott Wood2011-10-062-0/+87
| | | | | | | | | Share the TLB array with KVM. This allows us to set the initial TLB both on initial boot and reset, is useful for debugging, and could eventually be used to support migration. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
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