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* ppc: Correct BookE tlb readsEdgar E. Iglesias2011-01-211-1/+1
| | | | | | | Call the tlb read helper (and not the write helper) for tlb reads. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* target-ppc: fix wrong NaN testsAurelien Jarno2011-01-201-17/+28
| | | | | | | | | | Some tests in FPU emulation code were wrongly using float64_is_nan() before commit 185698715dfb18c82ad2a5dbc169908602d43e81, and wrongly using float64_is_quiet_nan() after. Fix them by using float64_is_any_nan() instead. Reviewed-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-ppc: fix sNaN propagationAurelien Jarno2011-01-201-69/+78
| | | | | | | | | | | | | | The current FPU code returns 0.0 if one of the operand is a signaling NaN and the VXSNAN exception is disabled. fload_invalid_op_excp() doesn't return a qNaN in case of a VXSNAN exception as the operand should be propagated instead of a new qNaN to be generated. Fix that by calling fload_invalid_op_excp() only for the exception generation (if enabled), and use the softfloat code to correctly compute the result. Reviewed-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-ppc: use float32_is_any_nan()Aurelien Jarno2011-01-061-3/+2
| | | | | | | | Use the new function float32_is_any_nan() instead of float32_is_quiet_nan() || float32_is_signaling_nan(). Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-ppc: fix default qNaNAurelien Jarno2011-01-061-2/+2
| | | | | | | On PPC the default qNaN doesn't have the sign bit set. Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-ppc: remove PRECISE_EMULATION defineAurelien Jarno2011-01-062-50/+11
| | | | | | | | | | The PRECISE_EMULATION is "hardcoded" to one in target-ppc/exec.h and not something easily tunable. Remove it and non-precise emulation code as it doesn't make a noticeable difference in speed. People wanting speed improvement should use softfloat-native instead. Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* softfloat: Rename float*_is_nan() functions to float*_is_quiet_nan()Peter Maydell2011-01-021-29/+29
| | | | | | | | | | | | | | | | The softfloat functions float*_is_nan() were badly misnamed, because they return true only for quiet NaNs, not for all NaNs. Rename them to float*_is_quiet_nan() to more accurately reflect what they do. This change was produced by: perl -p -i -e 's/_is_nan/_is_quiet_nan/g' $(git grep -l is_nan) (with the results manually checked.) Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Nathan Froyd <froydnj@codesourcery.com> Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Fix translation of unary PPC/SPE instructions (efdneg etc.).Mike Pall2010-12-311-18/+21
| | | | | Signed-off-by: Mike Pall <mike-lp10@luajit.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* ppc: kvm: fix signedness warningAlexander Graf2010-12-081-1/+1
| | | | | | | | I get a warning on a signed comparison with an unsigned variable, so let's make the variable signed and be happy. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
* target-xxx: Use fprintf_function (format checking)Stefan Weil2010-10-303-11/+9
| | | | | | | | | | | | | fprintf_function uses format checking with GCC_FMT_ATTR. Format errors were fixed in * target-i386/helper.c * target-mips/translate.c * target-ppc/translate.c Cc: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Stefan Weil <weil@mail.berlios.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* ppc: avoid write only variablesBlue Swirl2010-10-131-3/+3
| | | | | | | | | | | | | | Compiling with GCC 4.6.0 20100925 produced warnings: /src/qemu/target-ppc/op_helper.c: In function 'helper_icbi': /src/qemu/target-ppc/op_helper.c:351:14: error: variable 'tmp' set but not used [-Werror=unused-but-set-variable] /src/qemu/target-ppc/op_helper.c: In function 'do_6xx_tlb': /src/qemu/target-ppc/op_helper.c:3805:28: error: variable 'EPN' set but not used [-Werror=unused-but-set-variable] /src/qemu/target-ppc/op_helper.c: In function 'do_74xx_tlb': /src/qemu/target-ppc/op_helper.c:3838:28: error: variable 'EPN' set but not used [-Werror=unused-but-set-variable] Fix by adding a dummy cast so that the variable is not unused. Delete tmp. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* ppc: remove video.xBlue Swirl2010-10-132-14/+0
| | | | | | | | | Only Mac-on-Linux stuff used video.x, OpenBIOS does not need it. Remove video.x MoL hacks. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* ppc: Minor 40x MMU fixesJohn Clark2010-10-052-27/+49
| | | | | | | | | * Fix swapped reading of tlblo/hi. * Fix tlb exec permissions Signed-off-by: John Clark <clarkjc@runbox.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* powerpc: Add a virtex5 ml507 refdesign boardEdgar E. Iglesias2010-09-301-0/+4
| | | | | Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* powerpc: Add a ppc-440x5 Xilinx modelEdgar E. Iglesias2010-09-301-2/+4
| | | | | | | | Add a powerpc 440x5 with the model ID on the Xilinx virtex5. Connect the 440x5 to the 40x interrupt logic. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* powerpc: Improve emulation of the BookE MMUEdgar E. Iglesias2010-09-242-8/+33
| | | | | | | Improve the emulation of the BookE MMU to be able to boot linux on virtex5 boards. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* PPC: Suppress gcc warnings with -Wtype-limitsBlue Swirl2010-09-181-25/+25
| | | | | | | | The hack added by c5b76b381081680633e2e0a91216507430409fb2 was not enough to avoid warnings with gcc flag -Wtype-limits. Add a new macro to fix both problems. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* PPC: Redesign interrupt trigger pathAlexander Graf2010-09-151-51/+29
| | | | | | | | | | | | | | According to the Book3S spec, the interrupt context starts with an MSR value that is rather simple. If we leave out the HV case, it's almost always 0. To reflect this, let's redesign the way that MSR value gets calculated. Using this, we also squash the bug where MSR_POW can slip through into the interrupt handler MSR. Reported-by: Thomas Monjalon <thomas.monjalon@openwide.fr> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* PPC: Enable hint bits for lwarx/ldarxAlexander Graf2010-09-151-2/+2
| | | | | | | | | | | | | The lwarx and ldarx instructions have a bit to give some hint to the CPU which is safe to ignore. We currently refuse to accept any instruction with that bit set, as it used to be declared MBZ. Let's remove the reserved bit and make the instruction work as expected. This fixes Linux boot for ppc64. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Andreas Färber <andreas.faerber@web.de> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* powerpc: Avoid TLB related log spammingEdgar E. Iglesias2010-09-111-1/+0
| | | | | | Invalid TLB entries are normal and should not spam the log. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
* KVM: PPC: Add level based interrupt logicAlexander Graf2010-09-052-2/+48
| | | | | | | | | | | | | | | | | | | | | | KVM on PowerPC used to have completely broken interrupt logic. Usually, interrupts work by having a PIC that pulls a line up/down, so the CPU knows that an interrupt is active. This line stays active until some action is done to the PIC to release the line. On KVM for PPC, we just checked if there was an interrupt pending and pulled a line in the kernel module. We never released it though, hoping that kernel space would just declare an interrupt as released when injected - which is wrong. To fix this, we need to completely redesign the interrupt injection logic. Whenever an interrupt line gets triggered, we need to notify kernel space that the line is up. Whenever it gets released, we do the same. This way we can assure that the interrupt state is always known to kernel space. This fixes random stalls in KVM guests on PowerPC that were waiting for an interrupt while everyone else thought they received it already. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Add PV hypercall transport through fw_cfgAlexander Graf2010-08-262-0/+33
| | | | | | | | | | | On KVM for PPC we need to tell the guest which instructions to use when doing a hypercall. The clean way to do this is to go through an ioctl from userspace and passing it on to the guest using the device tree. So let's do the qemu part here: read out the hypercall and pass it on to the guest's fw_cfg so openBIOS can read it out and expose it again. Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: fix power mode checking on 7400/7410Aurelien Jarno2010-07-191-2/+2
| | | | | Only the PowerPC 7440/7450 family don't support DOZE mode. PowerPC 7400 and 7410 support it.
* target-ppc: add vexptefp instructionAurelien Jarno2010-07-133-0/+13
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* remove exec-all.h inclusion from cpu.hPaolo Bonzini2010-07-031-1/+0
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* move cpu_pc_from_tb to target-*/exec.hPaolo Bonzini2010-07-032-5/+5
| | | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.Richard Henderson2010-06-161-0/+1
| | | | | | | | | | | | | | | | | | Some hosts (amd64, ia64) have an ABI that ignores the high bits of the 64-bit register when passing 32-bit arguments. Others require the value to be properly sign-extended for the type. I.e. "int32_t" must be sign-extended and "uint32_t" must be zero-extended to 64-bits. To effect this, extend the "sizemask" parameter to tcg_gen_callN to include the signedness of the type of each parameter. If the tcg target requires it, extend each 32-bit argument into a 64-bit temp and pass that to the function call. This ABI feature is required by sparc64, ppc64 and s390x. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-ppc: remove useless lineThomas Monjalon2010-05-311-1/+0
| | | | | | | | | This line was a bit clear. The next lines set or reset this bit (LE) depending of another bit (ILE). So the first line is useless. Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-ppc: fix RFI by clearing some bits of MSRThomas Monjalon2010-05-312-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 2ada0ed, "Return From Interrupt" is broken for PPC processors because some interrupt specifics bits of SRR1 are copied to MSR. SRR1 is a save of MSR during interrupt. During RFI, MSR must be restored from SRR1. But some bits of SRR1 are interrupt-specific and are not used for MSR saving. This is the specification (ISA 2.06) at chapter 6.4.3 (Interrupt Processing): "2. Bits 33:36 and 42:47 of SRR1 or HSRR1 are loaded with information specific to the interrupt type. 3. Bits 0:32, 37:41, and 48:63 of SRR1 or HSRR1 are loaded with a copy of the corresponding bits of the MSR." Below is a representation of MSR bits which are not saved: 0:15 16:31 32 33:36 37:41 42:47 48:63 ——— | ——— | — X X X X — — — — — X X X X X X | ———— 0000 0000 | 7 | 8 | 3 | F | 0000 History: In the initial Qemu implementation (e1833e1), the mask 0x783F0000 was used for saving MSR in SRR1. But all the bits 32:47 were cleared during RFI restoring. This was wrong. The commit 2ada0ed explains that this breaks Altivec. Indeed, bit 38 (for Altivec support) must be saved and restored. The change of 2ada0ed was to restore all the bits of SRR1 to MSR. But it's also wrong. Explanation: As an example, let's see what's happening after a TLB miss. According to the e300 manual (E300CORERM table 5-6), the TLB miss interrupts set the bits 44-47 for KEY, I/D, WAY and S/L. These bits are specifics to the interrupt and must not be copied into MSR at the end of the interrupt. With the current implementation, a TLB miss overwrite bits POW, TGPR and ILE. Fix: It shouldn't be needed to filter-out bits on MSR saving when interrupt occurs. Specific bits overwrite MSR ones in SRR1. But at the end of interrupt (RFI), specifics bits must be cleared before restoring MSR from SRR1. The mask 0x783F0000 apply here. Discussion: The bits of the mask 0x783F0000 are cleared after an interrupt. I cannot find a specification which talks about this but I assume it is the truth since Linux can run this way. Maybe it's not perfect but it's better (works for e300). Signed-off-by: Thomas Monjalon <thomas@monjalon.net> Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Fix %lld or %llx printf format useBlue Swirl2010-05-221-3/+4
| | | | Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* PPC/KVM: make iothread workAlexander Graf2010-05-181-15/+15
| | | | | | | | | | | | | | | | When running with --enable-io-thread the timer we have doesn't help, because it doesn't wake up the CPU thread. So instead we need to actually kick it. While at it I refined the logic a bit to not dumbly trigger a timer every 500ms, but rather do it more often after an interrupt got injected. If there's no level based interrupt to be expected, we don't need the timer anyways. This makes qemu-system-ppc with --enable-io-thread work when using KVM. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Do not stop VM if emulation failed in userspace.Gleb Natapov2010-05-111-0/+5
| | | | | | | | | Continue vcpu execution in case emulation failure happened while vcpu was in userspace. In this case #UD will be injected into the guest allowing guest OS to kill offending process and continue. Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* kvm: enable smp > 1Marcelo Tosatti2010-05-111-0/+5
| | | | | | | Process INIT/SIPI requests and enable -smp > 1. Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by: Avi Kivity <avi@redhat.com>
* target-ppc: Remove duplicate cpu log.Richard Henderson2010-05-051-2/+0
| | | | | | | Logging for -d cpu is done in generic code. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* ppc: remove dead assignments, spotted by clang analyzerBlue Swirl2010-04-252-4/+10
| | | | | | Value stored is never read. Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* PPC: avoid function pointer type mismatch, spotted by clangBlue Swirl2010-04-181-5/+3
| | | | | | | | | | | | | | | Fixes clang errors: CC ppc-softmmu/translate.o /src/qemu/target-ppc/translate.c:3748:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *') if (likely(read_cb != SPR_NOACCESS)) { /src/qemu/target-ppc/translate.c:3748:28: note: instantiated from: if (likely(read_cb != SPR_NOACCESS)) { /src/qemu/target-ppc/translate.c:3903:13: error: comparison of distinct pointer types ('void (*)(void *, int, int)' and 'void *') if (likely(write_cb != SPR_NOACCESS)) { /src/qemu/target-ppc/translate.c:3903:29: note: instantiated from: if (likely(write_cb != SPR_NOACCESS)) { Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-ppc: generic PowerPC TBLDmitry Ilyevsky2010-03-261-4/+4
| | | | | | | | | | Time base SPRs TBL/TBU should be accessible in user/priv modes for reading as specified in POWER ISA documentation. Therefore SPRs permissions were changed in gen_tbl function. Signed-off-by: Dmitry Ilyevsky <ilyevsky@gmail.com> Acked-by: Alexander Graf <agraf@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Large page TLB flushPaul Brook2010-03-171-3/+4
| | | | | | | | | | | | | | | | | | QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com>
* Target specific usermode cleanupPaul Brook2010-03-121-0/+6
| | | | | | Disable various target specific code that is only relevant to system emulation. Signed-off-by: Paul Brook <paul@codesourcery.com>
* Remove cpu_get_phys_page_debug from userspace emulationPaul Brook2010-03-121-5/+0
| | | | | | cpu_get_phys_page_debug makes no sense for userspace emulation, so remove it. Signed-off-by: Paul Brook <paul@codesourcery.com>
* Move TARGET_PHYS_ADDR_SPACE_BITS to target-*/cpu.h.Richard Henderson2010-03-121-0/+17
| | | | | | | | | | Removes a set of ifdefs from exec.c. Introduce TARGET_VIRT_ADDR_SPACE_BITS for all targets other than Alpha. This will be used for page_find_alloc, which is supposed to be using virtual addresses in the first place. Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-ppc: fix evsrwu and evsrws (second try)Aurelien Jarno2010-03-111-2/+2
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-ppc: fix evsrwu and evsrwsAurelien Jarno2010-03-111-2/+2
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-ppc: fix evslw instructionAurelien Jarno2010-03-111-1/+1
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* KVM: Rework VCPU state writeback APIJan Kiszka2010-03-042-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This grand cleanup drops all reset and vmsave/load related synchronization points in favor of four(!) generic hooks: - cpu_synchronize_all_states in qemu_savevm_state_complete (initial sync from kernel before vmsave) - cpu_synchronize_all_post_init in qemu_loadvm_state (writeback after vmload) - cpu_synchronize_all_post_init in main after machine init - cpu_synchronize_all_post_reset in qemu_system_reset (writeback after system reset) These writeback points + the existing one of VCPU exec after cpu_synchronize_state map on three levels of writeback: - KVM_PUT_RUNTIME_STATE (during runtime, other VCPUs continue to run) - KVM_PUT_RESET_STATE (on synchronous system reset, all VCPUs stopped) - KVM_PUT_FULL_STATE (on init or vmload, all VCPUs stopped as well) This level is passed to the arch-specific VCPU state writing function that will decide which concrete substates need to be written. That way, no writer of load, save or reset functions that interact with in-kernel KVM states will ever have to worry about synchronization again. That also means that a lot of reasons for races, segfaults and deadlocks are eliminated. cpu_synchronize_state remains untouched, just as Anthony suggested. We continue to need it before reading or writing of VCPU states that are also tracked by in-kernel KVM subsystems. Consequently, this patch removes many cpu_synchronize_state calls that are now redundant, just like remaining explicit register syncs. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
* target-ppc: don't print invalid opcode messages on the consoleAurelien Jarno2010-02-281-11/+0
| | | | | | | | Invalid opcode messages can be perfectly normal, for example if this code is never executed. Don't print an error message on the console, but keep the message in the log for debugging purposes. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Revert "target-ppc: stop translation after a trap instruction"Aurelien Jarno2010-02-281-12/+8
| | | | This reverts commit 6454e7be1b2504533f7ffb190d54ebe2993cb434.
* target-ppc: stop translation after a trap instructionAurelien Jarno2010-02-281-8/+12
| | | | Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-ppc: fix SPE evsplat* instructionsNathan Froyd2010-02-271-2/+2
| | | | | | | | | The shifts in the gen_evsplat* functions were expecting rA to be masked, not extracted, and so used the wrong shift amounts to sign-extend or pad with zeroes. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-ppc: fix SPE evcmp* instructionsNathan Froyd2010-02-271-4/+4
| | | | | | | | | | | | The CRF_{CH,CL,CH_OR_CL,CH_AND_CL} constants were all off by one bit position. Because of this, the SPE evcmp* family of instructions would store values in the result condition register that were also off by one bit position. Fixed by using the CRF_{LT,GT,EQ,SO} constants for the shift amounts. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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