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* target-ppc: Split out SO, OV, CA fields from XERRichard Henderson2013-02-231-2/+2
| | | | | | | | In preparation for more efficient setting of these fields. Cc: Alexander Graf <agraf@suse.de> Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* cpu: Add CPUArchState pointer to CPUStateAndreas Färber2013-02-161-0/+2
| | | | | | | | | | | | The target-specific ENV_GET_CPU() macros have allowed us to navigate from CPUArchState to CPUState. The reverse direction was not supported. Avoid introducing CPU_GET_ENV() macros by initializing an untyped pointer that is initialized in derived instance_init functions. The field may not be called "env" due to it being poisoned. Acked-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Move TCG initialization to PowerPCCPU initfnAndreas Färber2013-02-161-5/+4
| | | | | | Ensures that a QOM-created PowerPCCPU is usable. Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Update PowerPCCPU to QOM realizefnAndreas Färber2013-02-161-3/+9
| | | | | | | | Adapt ppc_cpu_realize() signature, hook it up to DeviceClass and set realized = true in cpu_ppc_init(). Reviewed-by: Eduardo Habkost <ehabkost@redhat.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* error: Strip trailing '\n' from error string arguments (again)Markus Armbruster2013-02-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 6daf194d and be62a2eb got rid of a bunch, but they keep coming back. Tracked down with this Coccinelle semantic patch: @r@ expression err, eno, cls, fmt; position p; @@ ( error_report(fmt, ...)@p | error_set(err, cls, fmt, ...)@p | error_set_errno(err, eno, cls, fmt, ...)@p | error_setg(err, fmt, ...)@p | error_setg_errno(err, eno, fmt, ...)@p ) @script:python@ fmt << r.fmt; p << r.p; @@ if "\\n" in str(fmt): print "%s:%s:%s:%s" % (p[0].file, p[0].line, p[0].column, fmt) Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-id: 1360354939-10994-4-git-send-email-armbru@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* cpu: do not use object_deletePaolo Bonzini2013-02-011-1/+1
| | | | | | | | CPUs are never added to the composition tree, so delete is achieved simply by removing the last references to them. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* PPC: Unify dcbzl code pathAlexander Graf2013-02-011-5/+5
| | | | | | | | | | | | | | | | | The bit that makes a dcbz instruction a dcbzl instruction was declared as reserved in ppc32 ISAs. However, hardware simply ignores the bit, making code valid if it simply invokes dcbzl instead of dcbz even on 750 and G4. Thus, mark the bit as unreserved so that we properly emulate a simple dcbz in case we're running on non-G5s. While at it, also refactor the code to check the 970 special case during runtime. This way we don't need to differenciate between a 970 dcbz and any other dcbz anymore. We also allow for future improvements to add e500mc dcbz handling. Reported-by: Amadeusz Sławiński <amade@asmblr.net> Signed-off-by: Alexander Graf <agraf@suse.de>
* cpu: Add model resolution support to CPUClassAndreas Färber2013-01-271-0/+2
| | | | | | | | | Introduce CPUClass::class_by_name and add a default implementation. Hook up the alpha and ppc implementations. Introduce a wrapper function cpu_class_by_name(). Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Give a meaningful error if too many threads are specifiedMike Qiu2013-01-251-0/+12
| | | | | | | | | | | | | | Currently the target-ppc tcg code only supports a single thread. You can specify more, but they're treated identically to multiple cores. On KVM we obviously can't support more threads than the hardware; if more are specified it will cause strange and cryptic errors. This patch clarifies the situation by giving a simple meaningful error if more threads are specified than we can support. Signed-off-by: Mike Qiu <qiudayu@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Provide zero SVR for -cpu e500mc and e5500Alexander Graf2013-01-181-2/+2
| | | | | | | | | | Even though our -cpu types for e500mc and e5500 are no real CPUs that actually have version registers, a guest might still want to access said version register and that has to succeed for a guest to be happy. So let's expose a zero SVR value on E500_SVR SPR reads. Signed-off-by: Alexander Graf <agraf@suse.de>
* cpu: Move cpu_index field to CPUStateAndreas Färber2013-01-151-4/+6
| | | | | | | | | | | | | Note that target-alpha accesses this field from TCG, now using a negative offset. Therefore the field is placed last in CPUState. Pass PowerPCCPU to [kvm]ppc_fixup_cpu() to facilitate this change. Move common parts of mips cpu_state_reset() to mips_cpu_reset(). Acked-by: Richard Henderson <rth@twiddle.net> (for alpha) [AF: Rebased onto ppc CPU subclasses and openpic changes] Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Slim conversion of model definitions to QOM subclassesAndreas Färber2013-01-071-107/+238
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the model list is highly macrofied, keep ppc_def_t for now and save a pointer to it in PowerPCCPUClass. This results in a flat list of subclasses including aliases, to be refined later. Move cpu_ppc_init() to translate_init.c and drop helper.c. Long-term the idea is to turn translate_init.c into a standalone cpu.c. Inline cpu_ppc_usable() into type registration. Split cpu_ppc_register() in two by code movement into the initfn and by turning the remaining part into a realizefn. Move qemu_init_vcpu() call into the new realizefn and adapt create_ppc_opcodes() to return an Error. Change ppc_find_by_pvr() -> ppc_cpu_class_by_pvr(). Change ppc_find_by_name() -> ppc_cpu_class_by_name(). Turn -cpu host into its own subclass. This requires to move the kvm_enabled() check in ppc_cpu_class_by_name() to avoid the class being found via the normal name lookup in the !kvm_enabled() case. Turn kvmppc_host_cpu_def() into the class_init and add an initfn that asserts KVM is in fact enabled. Implement -cpu ? and the QMP equivalent in terms of subclasses. This newly exposes -cpu host to the user, ordered last for -cpu ?. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Bring EPR support closer to realityAlexander Graf2013-01-071-6/+1
| | | | | | | | | | | | | | We already used to support the external proxy facility of FSL MPICs, but only implemented it halfway correctly. This patch adds support for * dynamic enablement of the EPR facility * interrupt acknowledgement only when the interrupt is delivered This way the implementation now is closer to real hardware. Signed-off-by: Alexander Graf <agraf@suse.de>
* softmmu: move include files to include/sysemu/Paolo Bonzini2012-12-191-2/+2
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-1/+1
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* build: kill libdis, move disassemblers to disas/Paolo Bonzini2012-12-191-1/+1
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-ppc: Rework storage of VPA registration stateDavid Gibson2012-10-291-3/+4
| | | | | | | | | | | | | | | | | | | | | With PAPR guests, hypercalls allow registration of the Virtual Processor Area (VPA), SLB shadow and dispatch trace log (DTL), each of which allow for certain communication between the guest and hypervisor. Currently, we store the addresses of the three areas and the size of the dtl in CPUPPCState. The SLB shadow and DTL are variable sized, with the size being retrieved from within the registered memory area at the hypercall time. This size can later be overwritten with other information, however, so we need to save the size as of registration time. We already do this for the DTL, but not for the SLB shadow, so this patch fixes that. In addition, we change the storage of the VPA information to use fixed size integer types which will make life easier for syncing this data with KVM, which we will need in future. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: 440: Emulate DCBR0Alexander Graf2012-10-291-1/+1
| | | | | | | The DCBR0 register on 440 is used to implement system reset. The same register is used on 405 as well, so just reuse the code. Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc/pseries: Reset VPA registration on CPU resetDavid Gibson2012-10-051-0/+8
| | | | | | | | | | | | | | The ppc specific CPU state contains several variables which track the VPA, SLB shadow and dispatch trace log. These are structures shared between OS and hypervisor that are used on the pseries machine to track various per-CPU quantities. The address of these structures needs to be registered by the guest on each boot, however currently this registration is not cleared when we reset the cpu. This patch corrects this bug. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* win32: provide separate macros for weak decls and definitionsAnthony Liguori2012-08-151-2/+2
| | | | | | | | mingw32 seems to want the declaration to also carry the weak attribute. Strangely, gcc on Linux absolutely does not want the declaration to be marked as weak. This may not be the right fix, but it seems to do the trick. Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* target-ppc: add implementation of query-cpu-definitions (v2)Anthony Liguori2012-08-131-0/+26
| | | | | Signed-off-by: Anthony Liguori <aliguori@us.ibm.com> Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
* target-ppc: Fix 2nd parameter for tcg_gen_shri_tlStefan Weil2012-06-241-1/+1
| | | | | | | This fixes a compiler error when QEMU was configured with --enable-debug. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: BookE: Support 32 and 64 bit wide MAS2Alexander Graf2012-06-241-1/+18
| | | | | | | | The MAS registers on BookE are all 32 bit wide, except for MAS2, which can hold up to 64 bit on 64 bit capable CPUs. Reflect this in the SPR setting code, so that the guest can never write invalid values in them. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Extract SPR dump generation into its own functionAlexander Graf2012-06-241-12/+18
| | | | | | | This patch moves the debug #ifdef'ed SPR trace generation into its own function, so we can call it from multiple places. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Add e5500 CPU targetAlexander Graf2012-06-241-3/+93
| | | | | | | This patch adds e5500's CPU initialization to the TCG CPU initialization code. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: BookE: Make ivpr selectable by CPU typeAlexander Graf2012-06-241-4/+5
| | | | | | | | IVPR can either hold 32 or 64 bit addresses, depending on the CPU type. Let the CPU initialization function pass in its mask itself, so we can easily extend it. Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc64: Rudimentary Support for extra page sizes on server CPUsBenjamin Herrenschmidt2012-06-241-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | More recent Power server chips (i.e. based on the 64 bit hash MMU) support more than just the traditional 4k and 16M page sizes. This can get quite complicated, because which page sizes are supported, which combinations are supported within an MMU segment and how these page sizes are encoded both in the SLB entry and the hash PTE can vary depending on the CPU model (they are not specified by the architecture). In addition the firmware or hypervisor may not permit use of certain page sizes, for various reasons. Whether various page sizes are supported on KVM, for example, depends on whether the PR or HV variant of KVM is in use, and on the page size of the memory backing the guest's RAM. This patch adds information to the CPUState and cpu defs to describe the supported page sizes and encodings. Since TCG does not yet support any extended page sizes, we just set this to NULL in the static CPU definitions, expanding this to the default 4k and 16M page sizes when we initialize the cpu state. When using KVM, however, we instead determine available page sizes using the new KVM_PPC_GET_SMMU_INFO call. For old kernels without that call, we use some defaults, with some guesswork which should do the right thing for existing HV and PR implementations. The fallback might not be correct for future versions, but that's ok, because they'll have KVM_PPC_GET_SMMU_INFO. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Avoid AREG0 for misc helpersBlue Swirl2012-06-241-6/+6
| | | | | | | | | Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Avoid AREG0 for timebase helpersBlue Swirl2012-06-241-19/+19
| | | | | | | | | Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Avoid AREG0 for MMU etc. helpersBlue Swirl2012-06-241-12/+12
| | | | | | | | | Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Fix up e500 cache size settingAlexander Graf2012-05-011-12/+14
| | | | | | | | | | | | When initializing the e500 code, we need to expose its cache line size for user and system mode, while the mmu details are only interesting for system emulation. Split the 2 switch statements apart, allowing us to #ifdef out the mmu parts for user mode emulation while keeping all cache information consistent. Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Init dcache and icache size for e500 user modeMeador Inge2012-04-151-1/+4
| | | | | | | | | | | | | commit f7aa558396dd0f6b7a2b22c05cb503c655854102 pulled the dcache and icache line size initialization inside of a '#if !defined(CONFIG_USER_ONLY)' block. This is not correct because instructions like 'dcbz' need the dcache size initialized even for user mode. Signed-off-by: Meador Inge <meadori@codesourcery.com> Cc: Varun Sethi <Varun.Sethi@freescale.com> [AF: Simplify #ifdefs by using cache line size 32 for *-user as before] Suggested-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: Fix type casts for w64 (uintptr_t)Stefan Weil2012-04-151-3/+3
| | | | | | | This changes nothing for other hosts. Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-ppc: QOM'ify CPU resetAndreas Färber2012-04-151-1/+45
| | | | | | | | | | Move code from cpu_state_reset() into ppc_cpu_reset(). Reorder #include of helper_regs.h to use it in translate_init.c. Adjust whitespace and add braces. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
* target-ppc: Start QOM'ifying CPU initAndreas Färber2012-04-151-0/+9
| | | | | | | Move code not dependent on ppc_def_t from cpu_ppc_init() into an initfn. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
* target-ppc: QOM'ify CPUAndreas Färber2012-04-151-0/+37
| | | | | | | | | | | Embed CPUPPCState as first member of PowerPCCPU. Distinguish between "powerpc-cpu", "powerpc64-cpu" and "embedded-powerpc-cpu". Let CPUClass::reset() call cpu_state_reset() for now. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: David Gibson <david@gibson.dropbear.id.au>
* target-ppc: Add hooks for handling tcg and kvm limitationsDavid Gibson2012-04-151-16/+35
| | | | | | | | | | | | | | | | | On target-ppc, our table of CPU types and features encodes the features as found on the hardware, regardless of whether these features are actually usable under TCG or KVM. We already have cases where the information from the cpu table must be fixed up to account for limitations in the emulation method we're using. e.g. TCG does not support the DFP and VSX instructions and KVM needs different numbering of the CPUs in order to tell it the correct thread to core mappings. This patch cleans up these hacks to handle emulation limitations by consolidating them into a pair of functions specifically for the purpose. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [AF: Style and typo fixes, rename new functions and drop ppc_def_t arg] Signed-off-by: Andreas Färber <afaerber@suse.de>
* Replace Qemu by QEMU in commentsStefan Weil2012-04-071-12/+12
| | | | | | | | | The official spelling is QEMU. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> [blauwirbel@gmail.com: fixed comment style in hw/sun4m.c] Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* ppc: Correctly define POWERPC_INSNS2_DEFAULTMeador Inge2012-03-151-2/+2
| | | | | | | | | | | | | 'POWERPC_INSNS2_DEFAULT' was defined incorrectly which was causing the opcode table creation code to erroneously register 'eieio' and 'mbar' for the "default" processor: ** ERROR: opcode 1a already assigned in opcode table 16 *** ERROR: unable to insert opcode [1f-16-1a] *** ERROR initializing PowerPC instruction 0x1f 0x16 0x1a Signed-off-by: Meador Inge <meadori@codesourcery.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Add PIR register to POWER7 CPUNathan Whitehorn2012-03-151-0/+5
| | | | | | | | | | The POWER7 emulation is missing the Processor Identification Register, mandatory in recent POWER CPUs, that is required for SMP on at least some operating systems (e.g. FreeBSD) to function properly. This patch copies the existing PIR code from the other CPUs that implement it. Signed-off-by: Nathan Whitehorn <nwhitehorn@freebsd.org> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC64: Add support for ldbrx and stdbrx instructionsThomas Huth2012-03-151-1/+1
| | | | | | | | | These instructions for loading and storing byte-swapped 64-bit values have been introduced in PowerISA 2.06. Signed-off-by: Thomas Huth <thuth@linux.vnet.ibm.com> Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
* target-ppc: Don't overuse CPUStateAndreas Färber2012-03-141-21/+21
| | | | | | | | | Scripted conversion: sed -i "s/CPUState/CPUPPCState/g" target-ppc/*.[hc] sed -i "s/#define CPUPPCState/#define CPUState/" target-ppc/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com>
* PPC: E500: Populate L1CFG0 SPRAlexander Graf2012-02-021-1/+4
| | | | | | | | | | | | When running Linux on e500 with powersave-nap enabled, Linux tries to read out the L1CFG0 register and calculates some things from it. Passing 0 there ends up in a division by 0, resulting in -1, resulting in badness. So let's populate the L1CFG0 register with reasonable defaults. That way guests aren't completely confused. Reported-by: Shrijeet Mukherjee <shm@cumulusnetworks.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: e500mc: Enable processor controlAlexander Graf2012-02-021-1/+1
| | | | | | | | The e500mc implements Embedded.Processor Control, so enable it and thus enable guests to IPI each other. This makes -smp work with -cpu e500mc. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: e500: msync is 440 only, e500 has real syncAlexander Graf2012-02-021-3/+3
| | | | | | | | The e500 CPUs don't use 440's msync which falls on the same opcode IDs, but instead use the real powerpc sync instruction. This is important, since the invalid mask differs between the two. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: e500mc: add missing IVORs to bitmapAlexander Graf2012-02-021-1/+5
| | | | | | | E500mc supports IVORs 36-41. Add them to the support mask. Drop SPE support too. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Add IVOR 38-42Alexander Graf2012-02-021-14/+15
| | | | | | | | Our code only knows IVORs up to 37. Add the new ones defined in ISA 2.06 from 38 - 42. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Andreas Färber <afaerber@suse.de>
* PPC: Enable 440EP CPU targetAlexander Graf2012-01-211-11/+5
| | | | | | | Now that we have 440 TLB emulation, we can also support running the 440EP CPU target in system emulation mode. Signed-off-by: Alexander Graf <agraf@suse.de>
* PPC: Add description for the Freescale e500mc core.Varun Sethi2012-01-031-6/+50
| | | | | | | | | | | | | This core is found on chips such as p4080, p3041, p2040, and p5020. More needs to be done to make this viable for TCG (such as missing SPRs and instructions), but this suffices to get KVM running with appropriate kernel support. Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> [scottwood@freescale.com: tweak some flags] Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* ppc: Alter CPU state to mask out TCG unimplemented instructions as appropriateDavid Gibson2011-10-311-3/+17
| | | | | | | | | | | | | | | | | | | The CPU state contains two bitmaps, initialized from the CPU spec which describes which instructions are implemented on the CPU. A couple of bits are defined which cover instructions (VSX and DFP) which are not currently implemented in TCG. So far, these are only used to handle the case of -cpu host because a KVM guest can use the instructions when the host CPU supports them. However, it's a mild layering violation to simply not include those bits in the CPU descriptions for those CPUs that do support them, just because we can't handle them in TCG. This patch corrects the situation, so that the instruction bits _are_ shown correctly in the cpu spec table, but are masked out from the cpu state in the non-KVM case. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Alexander Graf <agraf@suse.de>
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