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* target-ppc: Model e500v{1,2} CPUs more accuratelyaurel322009-02-091-102/+125
* target-ppc: Model SPE floating-point instructions more accuratelyaurel322009-02-091-9/+9
* targets: remove error handling from qemu_malloc() callers (Avi Kivity)aliguori2009-02-051-2/+0
* Add calls to initialize VSCR on appropriate machinesaurel322009-02-031-0/+22
* target-ppc: Add SPE register read/write using XMLaurel322009-01-241-0/+50
* target-ppc: Add Altivec register read/write using XMLaurel322009-01-241-0/+50
* target-ppc: Add float register read/write using XMLaurel322009-01-241-0/+32
* target-ppc: Include gdbstub.haurel322009-01-241-0/+1
* Update FSF address in GPL/LGPL boilerplateaurel322009-01-041-1/+1
* Use the ARRAY_SIZE() macro where appropriate.malc2008-12-221-3/+3
* target-ppc: rework exception codeaurel322008-12-111-3/+3
* target-ppc: convert SPR accesses to TCGaurel322008-12-071-132/+177
* Attached patch fixes a series of this warningblueswir12008-11-161-1/+1
* target-ppc: Convert XER accesses to TCGaurel322008-10-211-2/+2
* Suppress gcc 4.x -Wpointer-sign (included in -Wall) warningsblueswir12008-09-201-9/+9
* ppc: Convert ctr, lr moves to TCGaurel322008-09-141-4/+4
* Fix some warnings that would be generated by gcc -Wredundant-declsblueswir12008-08-301-2/+0
* Fix PowerPC 74xx definitions.j_mayer2007-12-101-47/+225
* Fix PowerPC 7xx definitions.j_mayer2007-11-211-132/+612
* Remove shared macro used to define PowerPC implementations instructions sets:j_mayer2007-11-191-172/+480
* PowerPC 620 MMU do not have the same exact behavior as standardj_mayer2007-11-191-3/+6
* New PowerPC CPU flag to define the decrementer and time-base source clock.j_mayer2007-11-191-39/+67
* Improve PowerPC instructions set dump.j_mayer2007-11-171-6/+44
* Add definitions for Freescale PowerPC implementations,j_mayer2007-11-171-1259/+2850
* Define Freescale cores specific MMU model, exceptions and input bus.j_mayer2007-11-171-4/+13
* A little more granularity in PowerPC instructions definition is neededj_mayer2007-11-171-21/+25
* Make the PowerPC MMU model, exception model and input bus modelj_mayer2007-11-171-4/+3
* Always make all PowerPC exception definitions visible.j_mayer2007-11-171-2/+0
* Reorganize PowerPC instructions categories, add icbi separate case.j_mayer2007-11-141-4/+6
* Add PVR and SPR definition for most embedded PowerPC from Freescale.j_mayer2007-11-121-59/+309
* Allow selection of PowerPC CPU giving a PVR.j_mayer2007-11-101-371/+420
* added cpu_model parameter to cpu_init()bellard2007-11-101-21/+11
* PowerPC 601 need specific callbacks for its BATs setup.j_mayer2007-11-041-1/+10
* Fix PowerPC high BATs access: BAT number was incorrect.j_mayer2007-11-031-3/+3
* PowerPC MMU and exception fixes:j_mayer2007-11-031-31/+31
* Implement power-management for all defined PowerPC CPUs.j_mayer2007-10-251-7/+172
* Allow selection of all defined PowerPC 74xx (aka G4) CPUs.j_mayer2007-10-251-36/+0
* There is no need of a specific MMU model for PowerPC 601.j_mayer2007-10-141-4/+1
* Remove synonymous in PowerPC MSR bits definitions.j_mayer2007-10-081-39/+171
* Real-mode only PowerPC 40x do not have any TLBs.j_mayer2007-10-081-1/+0
* Implement exception prefix feature for PowerPC 601.j_mayer2007-10-081-1/+1
* Add missing exception vectors for PowerPC 7x5.j_mayer2007-10-081-1/+27
* Work-around C89 and/or "old" gcc unspecified behavior (#if in macro calls).j_mayer2007-10-071-18/+9
* Reorganize the CPUPPCState structure to group features.j_mayer2007-10-071-3/+46
* Add MSR bits signification per PowerPC implementation flags (to be continued).j_mayer2007-10-071-0/+42
* Full implementation of PowerPC 64 MMU, just missing support for 1 TBj_mayer2007-10-051-22/+65
* Rename PowerPC MMUCSR0 and MMUCFG SPRs: those are not BookE specific.j_mayer2007-10-051-2/+2
* PowerPC hardware reset vector is now considered as part of the exception model.j_mayer2007-10-051-132/+30
* More cache tuning fixes:j_mayer2007-10-041-2/+22
* Make PowerPC cache line size implementation dependant.j_mayer2007-10-041-10/+236
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