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path: root/target-ppc/translate.c
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* PPC: Allow Rc bit to be set on mtsprAlexander Graf2015-11-121-1/+1
* target-*: Advance pc after recognizing a breakpointRichard Henderson2015-10-281-0/+5
* ppc: Add mmu_model defines for arch 2.03 and 2.07Benjamin Herrenschmidt2015-10-231-2/+2
* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-35/+5
* tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-2/+3
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-1/+5
* target-*: Introduce and use cpu_breakpoint_testRichard Henderson2015-10-071-9/+5
* target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-2/+2
* target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-3/+2
* tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-071-1/+1
* target-ppc: fix xscmpodp and xscmpudp decodingAurelien Jarno2015-09-201-2/+9
* disas: Remove uses of CPU envPeter Crosthwaite2015-06-221-1/+1
* tcg: Change translator-side labels to a pointerRichard Henderson2015-03-131-64/+59
* display cpu id dump stateTristan Gingold2015-03-091-2/+3
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-121-6/+3
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-121-1/+1
* Merge remote-tracking branch 'remotes/agraf/tags/signed-ppc-for-upstream' int...Peter Maydell2015-01-101-61/+210
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| * target-ppc: Mark SR() and gen_sync_exception() as !CONFIG_USER_ONLYPeter Maydell2015-01-071-0/+5
| * target-ppc: Introduce Privileged TM NoopsTom Musta2015-01-071-0/+38
| * target-ppc: Introduce tcheckTom Musta2015-01-071-0/+17
| * target-ppc: Introduce TM NoopsTom Musta2015-01-071-0/+38
| * target-ppc: Introduce tbeginTom Musta2015-01-071-0/+12
| * target-ppc: Introduce tm_enabled Bit to CPU StateTom Musta2015-01-071-0/+8
| * target-ppc: Eliminate set_fprf Argument From helper_compute_fprfTom Musta2015-01-071-7/+1
| * target-ppc: Eliminate set_fprf Argument From gen_compute_fprfTom Musta2015-01-071-15/+23
| * target-ppc: Fully Migrate to gen_set_cr1_from_fpscrTom Musta2015-01-071-22/+33
| * target-ppc: mffs. Should Set CR1 from FPSCR BitsTom Musta2015-01-071-1/+3
| * target-ppc: Fix Floating Point Move Instructions That Set CR1Tom Musta2015-01-071-20/+30
| * target-ppc: Load/Store Vector Element Storage AlignmentTom Musta2015-01-071-8/+14
* | gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
* | target-ppc: pass DisasContext to SPR generator functionsPaolo Bonzini2014-12-231-5/+5
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* target-ppc: Altivec's mtvscr Decodes Wrong RegisterTom Musta2014-11-201-1/+1
* target-ppc: Fix Altivec Round OpcodesTom Musta2014-11-041-6/+6
* ppc: do not look at the MMU index to detect PR/HV modePaolo Bonzini2014-11-041-88/+77
* target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64Pierre Mallard2014-11-041-10/+6
* ppc: compute mask from BI using right shiftPaolo Bonzini2014-11-041-3/+3
* ppc: rename gen_set_cr6_from_fpscrPaolo Bonzini2014-11-041-7/+7
* target-ppc: Implement mulldo with TCGTom Musta2014-09-081-2/+14
* target-ppc: Clean up mullwoTom Musta2014-09-081-8/+3
* target-ppc: Clean Up mullwTom Musta2014-09-081-3/+2
* target-ppc: Optimize rlwnm MB=0 ME=31Tom Musta2014-09-081-22/+34
* target-ppc: Optimize rlwinm MB=0 ME=31Tom Musta2014-09-081-0/+6
* target-ppc: Special Case of rlwimi Should Use DepositTom Musta2014-09-081-6/+3
* target-ppc: Bug Fix: srawiTom Musta2014-09-081-1/+1
* target-ppc: Bug Fix: mullwTom Musta2014-09-081-0/+11
* target-ppc: Bug Fix: mullwoTom Musta2014-09-081-0/+9
* target-ppc: Bug Fix: rlwimiTom Musta2014-09-081-5/+7
* target-ppc: Bug Fix: rlwnmTom Musta2014-09-081-9/+9
* target-ppc: Bug Fix: rlwinmTom Musta2014-09-081-5/+3
* trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova2014-08-121-0/+3
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