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path: root/target-ppc/translate.c
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* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-051-0/+1
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-281-3/+2
* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-131-2/+2
* target-ppc: Use Additional Temporary in stqcx CaseTom Musta2014-03-051-3/+5
* target-ppc/translate.c: Use ULL suffix for 64 bit constantsPeter Maydell2014-03-051-2/+2
* target-ppc: Altivec 2.07: Vector Permute and Exclusive ORTom Musta2014-03-051-1/+6
* target-ppc: Altivec 2.07: Vector SHA Sigma InstructionsTom Musta2014-03-051-0/+24
* target-ppc: Altivec 2.07: AES InstructionsTom Musta2014-03-051-0/+29
* target-ppc: Altivec 2.07: Binary Coded Decimal InstructionsTom Musta2014-03-051-4/+41
* target-ppc: Altivec 2.07: Vector Polynomial Multiply SumTom Musta2014-03-051-0/+8
* target-ppc: Altivec 2.07: Vector Gather Bits by BytesTom Musta2014-03-051-0/+2
* target-ppc: Altivec 2.07: Doubleword ComparesTom Musta2014-03-051-3/+13
* target-ppc: Altivec 2.07: vbpermq InstructionTom Musta2014-03-051-0/+2
* target-ppc: Altivec 2.07: Quadword Addition and SubtracationTom Musta2014-03-051-0/+18
* target-ppc: Altivec 2.07: Vector Doubleword Rotate and Shift InstructionsTom Musta2014-03-051-0/+8
* target-ppc: Altivec 2.07: Vector Merge InstructionsTom Musta2014-03-051-0/+37
* target-ppc: Altivec 2.07: Unpack Signed Word InstructionsTom Musta2014-03-051-0/+4
* target-ppc: Altivec 2.07: Pack Doubleword InstructionsTom Musta2014-03-051-0/+8
* target-ppc: Altivec 2.07: Vector Min/Max Doubleword InstructionsTom Musta2014-03-051-0/+8
* target-ppc: Altivec 2.07: Vector Population Count InstructionsTom Musta2014-03-051-4/+18
* target-ppc: Altivec 2.07: Add Vector Count Leading ZeroesTom Musta2014-03-051-0/+9
* target-ppc: Altivec 2.07: vmuluw InstructionTom Musta2014-03-051-1/+4
* target-ppc: Altivec 2.07: Multiply Even/Odd Word InstructionsTom Musta2014-03-051-0/+8
* target-ppc: Altivec 2.07: Add/Subtract Unsigned Doubleword ModuloTom Musta2014-03-051-0/+4
* target-ppc: Altivec 2.07: Vector Logical InstructionsTom Musta2014-03-051-0/+11
* target-ppc: Altivec 2.07: Add Support for R-Form Dual InstructionsTom Musta2014-03-051-0/+35
* target-ppc: Altivec 2.07: Add Opcode Macro for VX Form InstructionsTom Musta2014-03-051-0/+5
* target-ppc: Altivec 2.07: Add Support for Dual Altivec InstructionsTom Musta2014-03-051-0/+24
* target-ppc: Altivec 2.07: Add GEN_VXFORM3Tom Musta2014-03-051-0/+19
* target-ppc: Add Store Quadword ConditionalTom Musta2014-03-051-0/+21
* target-ppc: Add Load Quadword and ReserveTom Musta2014-03-051-0/+37
* target-ppc: Store QuadwordTom Musta2014-03-051-16/+23
* target-ppc: Load QuadwordTom Musta2014-03-051-14/+22
* target-ppc: Add is_user_mode Utility RoutineTom Musta2014-03-051-0/+14
* target-ppc: Add bctar InstructionTom Musta2014-03-051-1/+10
* target-ppc: Fix xxpermdi When T==A or T==BTom Musta2014-03-051-8/+33
* target-ppc: add extended opcodes for dcbt/dcbtstCédric Le Goater2014-03-051-2/+2
* target-ppc: Add ISA2.06 lfiwzx InstructionTom Musta2014-03-051-0/+15
* target-ppc: Add ISA 2.06 ftsqrtTom Musta2014-03-051-0/+10
* target-ppc: Add ISA 2.06 ftdiv InstructionTom Musta2014-03-051-0/+13
* target-ppc: Add ISA 2.06 fcfid[u][s] InstructionsTom Musta2014-03-051-0/+9
* target-ppc: Add ISA2.06 Float to Integer InstructionsTom Musta2014-03-051-0/+12
* target-ppc: Add ISA 2.06 stbcx. and sthcx. InstructionsTom Musta2014-03-051-47/+44
* target-ppc: Add ISA2.06 lbarx, lharx InstructionsTom Musta2014-03-051-26/+24
* target-ppc: Add ISA 2.06 divwe[o] InstructionsTom Musta2014-03-051-0/+4
* target-ppc: Add ISA 2.06 divweu[o] InstructionsTom Musta2014-03-051-0/+5
* target-ppc: Add ISA2.06 divde[o] InstructionsTom Musta2014-03-051-1/+4
* target-ppc: Add ISA2.06 divdeu[o] InstructionsTom Musta2014-03-051-0/+21
* target-ppc: Add ISA2.06 bpermd InstructionTom Musta2014-03-051-0/+10
* target-ppc: Scalar Non-Signalling ConversionsTom Musta2014-03-051-0/+4
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