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path: root/target-ppc/cpu.h
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* cpu: make CPU_INTERRUPT_RESET available on all targetsPaolo Bonzini2014-05-131-3/+0
* PPC: Clean up DECR implementationAlexander Graf2014-04-081-0/+1
* target-ppc: Introduce powerisa-207-server flagAlexey Kardashevskiy2014-03-201-0/+2
* target-ppc: Reset SPRs on CPU resetAlexey Kardashevskiy2014-03-201-0/+1
* exec: Change cpu_abort() argument to CPUStateAndreas Färber2014-03-131-1/+1
* cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber2014-03-131-2/+2
* cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2014-03-131-8/+0
* target-ppc: add PowerPCCPU::cpu_dt_idAlexey Kardashevskiy2014-03-051-0/+18
* target-ppc: Fix htab_mask calculationAneesh Kumar K.V2014-03-051-0/+1
* target-ppc: Altivec 2.07: Update AVR StructureTom Musta2014-03-051-0/+4
* target-ppc: Altivec 2.07: Add Instruction FlagTom Musta2014-03-051-1/+4
* target-ppc: Add Load Quadword and ReserveTom Musta2014-03-051-0/+1
* target-ppc: Add Flag for ISA 2.07 Load/Store Quadword InstructionsTom Musta2014-03-051-1/+3
* target-ppc: Add Target Address SPR (TAR) to Power8Tom Musta2014-03-051-0/+1
* target-ppc: Add Flag for bctarTom Musta2014-03-051-2/+4
* target-ppc: Add Flag for Power ISA V2.06 Floating Point Test InstructionsTom Musta2014-03-051-1/+3
* target-ppc: Add Flag for ISA V2.06 Floating Point ConversionTom Musta2014-03-051-1/+4
* target-ppc: Add Flag for ISA2.06 Atomic InstructionsTom Musta2014-03-051-1/+4
* target-ppc: Add Flag for ISA2.06 Divide Extended InstructionsTom Musta2014-03-051-1/+4
* target-ppc: Add ISA2.06 bpermd InstructionTom Musta2014-03-051-1/+3
* target-ppc: VSX Stage 4: Add VSX 2.07 FlagTom Musta2014-03-051-1/+3
* target-ppc: fix SPR_CTRL/SPR_UCTRL register numbersAlexey Kardashevskiy2014-03-051-2/+2
* target-ppc: fix LPCR SPR numberAlexey Kardashevskiy2014-03-051-1/+1
* Add MSR VSX and Associated ExceptionTom Musta2013-12-201-0/+4
* Declare and Enable VSXTom Musta2013-12-201-1/+4
* target-ppc: Use #define for max slb entriesAneesh Kumar K.V2013-10-251-1/+2
* target-ppc: USE LPCR_ILE to control exception endian on POWER7Anton Blanchard2013-09-021-0/+2
* target-ppc: Convert ppc cpu savevm to VMStateDescriptionAlexey Kardashevskiy2013-07-291-5/+3
* cpu: Introduce CPUClass::synchronize_from_tb() for cpu_pc_from_tb()Andreas Färber2013-07-231-5/+0
* linux-user: Move cpu_clone_regs() and cpu_set_tls() into linux-userPeter Maydell2013-07-091-20/+0
* target-ppc: Introduce unrealizefn for PowerPCCPUAndreas Färber2013-07-011-1/+3
* PPC: Add MMU type for 2.06 with AMR but no TB pagesAlexander Graf2013-05-061-0/+3
* target-ppc: add instruction flags for Book I 2.05Aurelien Jarno2013-04-261-1/+3
* target-ppc: Add more stubs for POWER7 PMU registersDavid Gibson2013-04-261-0/+1
* PPC: Remove env->hreset_excp_prefixFabien Chouteau2013-04-261-1/+0
* target-ppc: Move ppc tlb_fill implementation into mmu_helper.cDavid Gibson2013-03-221-2/+0
* target-ppc: Split user only code out of mmu_helper.cDavid Gibson2013-03-221-1/+4
* mmu-hash64: Implement Virtual Page Class Key ProtectionDavid Gibson2013-03-221-2/+6
* mmu-hash*: Add header file for definitionsDavid Gibson2013-03-221-24/+0
* target-ppc: mmu_ctx_t should not be a global typeDavid Gibson2013-03-221-14/+0
* target-ppc: Disentangle BAT code for 32-bit hash MMUsDavid Gibson2013-03-221-2/+0
* target-ppc: Don't share get_pteg_offset() between 32 and 64-bitDavid Gibson2013-03-221-1/+0
* target-ppc: Disentangle hash mmu helper functionsDavid Gibson2013-03-221-3/+0
* target-ppc: Disentangle get_physical_address() pathsDavid Gibson2013-03-221-0/+2
* target-ppc: Disentangle find_pte()David Gibson2013-03-221-0/+2
* target-ppc: Disentangle pte_check()David Gibson2013-03-221-0/+2
* target-ppc: Move SLB handling into a mmu-hash64.cDavid Gibson2013-03-221-3/+0
* target-ppc: Trivial cleanups in mmu_helper.cDavid Gibson2013-03-221-3/+0
* target-ppc: Remove vestigial PowerPC 620 supportDavid Gibson2013-03-221-30/+0
* PPC/GDB: handle read and write of fpscrFabien Chouteau2013-03-221-0/+2
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