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path: root/target-ppc/cpu.h
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* target-ppc: Use macros in opcodes table handling codeBharata B Rao2014-11-041-1/+2
* target-ppc : Allow fc[tf]id[*] mnemonics for non TARGET_PPC64Pierre Mallard2014-11-041-1/+4
* target-ppc: Use cpu_exec_interrupt qom hookRichard Henderson2014-09-251-1/+0
* target-ppc: enable virtio endian ambivalent supportGreg Kurz2014-06-291-0/+2
* target-ppc: Add DFP to Emulated Instructions FlagTom Musta2014-06-271-1/+1
* spapr_hcall: Add address-translation-mode-on-interrupt resource in H_SET_MODEAlexey Kardashevskiy2014-06-161-1/+3
* target-ppc: Add POWER8's Event Based Branch (EBB) control SPRsAlexey Kardashevskiy2014-06-161-0/+7
* KVM: target-ppc: Enable TM state migrationAlexey Kardashevskiy2014-06-161-0/+14
* target-ppc: Add POWER8's TM SPRsAlexey Kardashevskiy2014-06-161-0/+10
* target-ppc: Add POWER8's MMCR2/MMCRS SPRsAlexey Kardashevskiy2014-06-161-0/+3
* target-ppc: Add POWER8's FSCR SPRAlexey Kardashevskiy2014-06-161-0/+16
* target-ppc: Add POWER8's TIR SPRAlexey Kardashevskiy2014-06-161-0/+1
* target-ppc: Add HID4 SPR for PPC970Alexey Kardashevskiy2014-06-161-0/+1
* target-ppc: Add PMC7/8 to 970 classAlexey Kardashevskiy2014-06-161-0/+4
* target-ppc: Add "POWER" prefix to MMCRA PMU registersAlexey Kardashevskiy2014-06-161-1/+2
* target-ppc: Copy and split gen_spr_7xx() for 970Alexey Kardashevskiy2014-06-161-0/+20
* target-ppc: Merge 970FX and 970MP into a single 970 classAlexey Kardashevskiy2014-06-161-0/+5
* target-ppc: Rename 7XX/60x/74XX/e600 PMU SPRsAlexey Kardashevskiy2014-06-161-20/+20
* PPC: e500: Merge 32 and 64 bit SPE emulationAlexander Graf2014-06-161-4/+0
* spapr: Limit threads per core according to current compatibility modeAlexey Kardashevskiy2014-06-161-0/+1
* target-ppc: Implement "compat" CPU optionAlexey Kardashevskiy2014-06-161-0/+11
* PPC: Properly emulate L1CSR0 and L1CSR1Alexander Graf2014-06-161-0/+12
* PPC: Add L1CFG1 SPR emulationAlexander Graf2014-06-161-0/+1
* PPC: Add definitions for GIVORsAlexander Graf2014-06-161-0/+6
* cpu: make CPU_INTERRUPT_RESET available on all targetsPaolo Bonzini2014-05-131-3/+0
* PPC: Clean up DECR implementationAlexander Graf2014-04-081-0/+1
* target-ppc: Introduce powerisa-207-server flagAlexey Kardashevskiy2014-03-201-0/+2
* target-ppc: Reset SPRs on CPU resetAlexey Kardashevskiy2014-03-201-0/+1
* exec: Change cpu_abort() argument to CPUStateAndreas Färber2014-03-131-1/+1
* cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber2014-03-131-2/+2
* cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2014-03-131-8/+0
* target-ppc: add PowerPCCPU::cpu_dt_idAlexey Kardashevskiy2014-03-051-0/+18
* target-ppc: Fix htab_mask calculationAneesh Kumar K.V2014-03-051-0/+1
* target-ppc: Altivec 2.07: Update AVR StructureTom Musta2014-03-051-0/+4
* target-ppc: Altivec 2.07: Add Instruction FlagTom Musta2014-03-051-1/+4
* target-ppc: Add Load Quadword and ReserveTom Musta2014-03-051-0/+1
* target-ppc: Add Flag for ISA 2.07 Load/Store Quadword InstructionsTom Musta2014-03-051-1/+3
* target-ppc: Add Target Address SPR (TAR) to Power8Tom Musta2014-03-051-0/+1
* target-ppc: Add Flag for bctarTom Musta2014-03-051-2/+4
* target-ppc: Add Flag for Power ISA V2.06 Floating Point Test InstructionsTom Musta2014-03-051-1/+3
* target-ppc: Add Flag for ISA V2.06 Floating Point ConversionTom Musta2014-03-051-1/+4
* target-ppc: Add Flag for ISA2.06 Atomic InstructionsTom Musta2014-03-051-1/+4
* target-ppc: Add Flag for ISA2.06 Divide Extended InstructionsTom Musta2014-03-051-1/+4
* target-ppc: Add ISA2.06 bpermd InstructionTom Musta2014-03-051-1/+3
* target-ppc: VSX Stage 4: Add VSX 2.07 FlagTom Musta2014-03-051-1/+3
* target-ppc: fix SPR_CTRL/SPR_UCTRL register numbersAlexey Kardashevskiy2014-03-051-2/+2
* target-ppc: fix LPCR SPR numberAlexey Kardashevskiy2014-03-051-1/+1
* Add MSR VSX and Associated ExceptionTom Musta2013-12-201-0/+4
* Declare and Enable VSXTom Musta2013-12-201-1/+4
* target-ppc: Use #define for max slb entriesAneesh Kumar K.V2013-10-251-1/+2
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