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* cpu: Replace do_interrupt() by CPUClass::do_interrupt methodAndreas Färber2013-03-121-1/+1
| | | | | | | | | | This removes a global per-target function and thus takes us one step closer to compiling multiple targets into one executable. It will also allow to override the interrupt handling for certain CPU families. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move halted and interrupt_request fields to CPUStateAndreas Färber2013-03-121-3/+1
| | | | | | | | | | Both fields are used in VMState, thus need to be moved together. Explicitly zero them on reset since they were located before breakpoints. Pass PowerPCCPU to kvmppc_handle_halt(). Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Introduce ENV_OFFSET macrosAndreas Färber2013-03-031-0/+2
| | | | | | | | | | | | Introduce ENV_OFFSET macros which can be used in non-target-specific code that needs to generate TCG instructions which reference CPUState fields given the cpu_env register that TCG targets set up with a pointer to the CPUArchState struct. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-openrisc: Update OpenRISCCPU to QOM realizefnAndreas Färber2013-02-161-2/+2
| | | | | | | | | | Update the openrisc_cpu_realize() signature, hook it up to DeviceClass::realize and set realized = true in cpu_openrisc_init(). qapi/error.h is now included through qdev and no longer needed. Signed-off-by: Andreas Färber <afaerber@suse.de> Cc: Jia Liu <proljc@gmail.com>
* fpu: move public header file to include/fpuPaolo Bonzini2012-12-191-1/+1
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* qom: move include files to include/qom/Paolo Bonzini2012-12-191-1/+1
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* exec: move include files to include/exec/Paolo Bonzini2012-12-191-3/+3
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* qapi: move include files to include/qobject/Paolo Bonzini2012-12-191-1/+1
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-openrisc: remove conflicting definitions from cpu.hAurelien Jarno2012-11-241-18/+0
| | | | | | | | | | | On an ARM host, the registers definitions from cpu.h clash with /usr/include/sys/ucontext.h. As there are unused, just remove them. Cc: Jia Liu <proljc@gmail.com> Cc: qemu-stable@nongnu.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber2012-10-311-1/+3
| | | | | | | | | | For target-mips also change the return type to bool. Make include paths for cpu-qom.h consistent for alpha and unicore32. Signed-off-by: Andreas Färber <afaerber@suse.de> [AF: Updated new target-openrisc function accordingly] Acked-by: Richard Henderson <rth@twiddle.net> (for alpha)
* Rename target_phys_addr_t to hwaddrAvi Kivity2012-10-231-5/+5
| | | | | | | | | | | | | | | target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* target-or32: Add linux user supportJia Liu2012-07-271-0/+12
| | | | | | | Add QEMU OpenRISC linux user support. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-or32: Add system instructionsJia Liu2012-07-271-0/+3
| | | | | | | Add OpenRISC system instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-or32: Add timer supportJia Liu2012-07-271-0/+22
| | | | | | | Add OpenRISC timer support. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-or32: Add PIC supportJia Liu2012-07-271-0/+3
| | | | | | | Add OpenRISC Programmable Interrupt Controller support. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-or32: Add interrupt supportJia Liu2012-07-271-1/+7
| | | | | | | Add OpenRISC interrupt support. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-or32: Add MMU supportJia Liu2012-07-271-1/+78
| | | | | | | Add OpenRISC MMU support. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* target-or32: Add target stubs and QOM cpuJia Liu2012-07-271-0/+335
Add OpenRISC target stubs, QOM cpu and basic machine. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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