hqemu - HQEMU

	Commit message (Collapse)	Author	Age	Files	Lines
*	cpu: Introduce CPUClass::gdb_{read,write}_register()	Andreas Färber	2013-07-27	1	-0/+1
\| \| \| \| \| \| \| \|	Completes migration of target-specific code to new target-*/gdbstub.c. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Signed-off-by: Andreas Färber <afaerber@suse.de>
*	target-or32: Add system instructions	Jia Liu	2012-07-27	1	-1/+1
\| \| \| \| \| \| \|	Add OpenRISC system instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
*	target-or32: Add float instruction helpers	Jia Liu	2012-07-27	1	-1/+2
\| \| \| \| \| \| \|	Add OpenRISC float instruction helpers. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
*	target-or32: Add int instruction helpers	Jia Liu	2012-07-27	1	-1/+1
\| \| \| \| \| \| \|	Add OpenRISC int instruction helpers. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
*	target-or32: Add exception support	Jia Liu	2012-07-27	1	-2/+2
\| \| \| \| \| \| \|	Add OpenRISC exception support. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
*	target-or32: Add interrupt support	Jia Liu	2012-07-27	1	-1/+1
\| \| \| \| \| \| \|	Add OpenRISC interrupt support. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
*	target-or32: Add target stubs and QOM cpu	Jia Liu	2012-07-27	1	-0/+3
	Add OpenRISC target stubs, QOM cpu and basic machine. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>