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| * target-mips: Fix formatting in `mips_defs'Maciej W. Rozycki2014-12-161-19/+21
| * target-mips: Fix formatting in `decode_extended_mips16_opc'Maciej W. Rozycki2014-12-161-1/+1
| * target-mips: Enable vectored interrupt support for the 74Kf CPUMaciej W. Rozycki2014-12-161-1/+1
| * target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processorsMaciej W. Rozycki2014-12-161-0/+41
| * target-mips: Make CP0.Config4 and CP0.Config5 registers signedMaciej W. Rozycki2014-12-161-4/+4
| * target-mips: Add 5KEc and 5KEf MIPS64r2 processorsMaciej W. Rozycki2014-12-161-0/+45
| * target-mips: Make CP1.FIR read-only here tooMaciej W. Rozycki2014-12-161-1/+1
| * target-mips: Correct the handling of register #72 on writesMaciej W. Rozycki2014-12-161-1/+1
* | qemu-log: add log category for MMU infoAntony Pavlov2014-12-161-2/+4
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* target-mips: kvm: do not use get_clock()Paolo Bonzini2014-12-151-1/+1
* target-mips: fix multiple TCG registers covering same dataYongbok Kim2014-11-071-5/+3
* mips: Ensure PC update with MTC0 single-steppingMaciej W. Rozycki2014-11-071-1/+1
* target-mips: fix for missing delay slot in BC1EQZ and BC1NEZLeon Alrae2014-11-071-0/+1
* mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bitsMaciej W. Rozycki2014-11-071-3/+5
* mips: Add macros for CP0.Config3 and CP0.Config4 bitsMaciej W. Rozycki2014-11-071-0/+13
* mips: Respect CP0.Status.CU1 for microMIPS FP branchesMaciej W. Rozycki2014-11-071-2/+7
* target-mips: add MSA support to mips32r5-genericYongbok Kim2014-11-031-2/+2
* target-mips: add MSA MI10 format instructionsYongbok Kim2014-11-033-5/+131
* target-mips: add MSA 2RF format instructionsYongbok Kim2014-11-033-0/+621
* target-mips: add MSA VEC/2R format instructionsYongbok Kim2014-11-033-0/+265
* target-mips: add MSA 3RF format instructionsYongbok Kim2014-11-033-0/+1699
* target-mips: add MSA ELM format instructionsYongbok Kim2014-11-033-0/+290
* target-mips: add MSA 3R format instructionsYongbok Kim2014-11-033-0/+963
* target-mips: add MSA BIT format instructionsYongbok Kim2014-11-033-0/+297
* target-mips: add MSA I5 format instructionYongbok Kim2014-11-033-0/+232
* target-mips: add MSA I8 format instructionsYongbok Kim2014-11-033-2/+156
* target-mips: add MSA branch instructionsYongbok Kim2014-11-031-114/+220
* target-mips: add msa_helper.cYongbok Kim2014-11-032-1/+50
* target-mips: add msa_reset(), global msa registerYongbok Kim2014-11-032-0/+90
* target-mips: add MSA opcode enumYongbok Kim2014-11-031-0/+245
* target-mips: stop translation after ctc1Yongbok Kim2014-11-031-0/+6
* target-mips: remove duplicated mips/ieee mapping functionYongbok Kim2014-11-033-9/+6
* target-mips: add MSA exceptionsYongbok Kim2014-11-031-0/+10
* target-mips: add MSA defines and data structureYongbok Kim2014-11-033-2/+52
* target-mips: enable features in MIPS64R6-generic CPULeon Alrae2014-11-031-2/+9
* target-mips: correctly handle access to unimplemented CP0 registerLeon Alrae2014-11-031-278/+260
* target-mips: add restrictions for possible values in registersLeon Alrae2014-11-031-17/+53
* target-mips: CP0_Status.CU0 no longer allows the user to access CP0Leon Alrae2014-11-031-1/+2
* target-mips: implement forbidden slotLeon Alrae2014-11-032-36/+76
* target-mips: add Config5.SBRILeon Alrae2014-11-032-3/+32
* target-mips: update cpu_save/cpu_load to support new registersLeon Alrae2014-11-032-2/+26
* target-mips: add BadInstr and BadInstrP supportLeon Alrae2014-11-034-11/+133
* target-mips: add TLBINV supportLeon Alrae2014-11-036-8/+92
* target-mips: add new Read-Inhibit and Execute-Inhibit exceptionsLeon Alrae2014-11-032-2/+28
* target-mips: update PageGrain and m{t,f}c0 EntryLo{0,1}Leon Alrae2014-11-035-5/+57
* target-mips: add RI and XI fields to TLB entryLeon Alrae2014-11-033-1/+29
* target-mips: distinguish between data load and instruction fetchLeon Alrae2014-11-031-11/+10
* target-mips: add KScratch registersLeon Alrae2014-11-032-0/+47
* target-mips: add ULL suffix in bitswap to avoid compiler warningLeon Alrae2014-10-241-6/+6
* target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACXPeter Maydell2014-10-141-19/+1
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