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* Fix CP0_IntCtl handling.ths2007-04-092-2/+6
* Proper handling of reserved bits in the context register.ths2007-04-091-1/+1
* Mark watchpoint features as unimplemented.ths2007-04-092-3/+9
* Catch unaligned sc/scd.ths2007-04-092-0/+10
* Fix exception handling cornercase for rdhwr.ths2007-04-092-37/+9
* Remove bogus mtc0 handling.ths2007-04-091-10/+0
* Unify IRQ handling.pbrook2007-04-071-0/+2
* cpu_get_phys_page_debug should return target_phys_addr_tj_mayer2007-04-071-2/+2
* Implement prefx.ths2007-04-071-1/+41
* Set proper BadVAddress value for unaligned instruction fetch.ths2007-04-071-1/+2
* Actually skip over delay slot for a non-taken branch likely.ths2007-04-071-2/+2
* Fix ins/ext cornercase.ths2007-04-071-4/+4
* Fix handling of ADES exceptions.ths2007-04-061-1/+3
* Save state for all CP0 instructions, they may throw a CPU exception.ths2007-04-063-16/+45
* fix branch delay slot cornercases.ths2007-04-052-3/+6
* Fix rotr immediate ops, mask shift/rotate arguments to their allowedths2007-04-053-48/+103
* Handle EBase properly.ths2007-04-051-1/+1
* Fix RDHWR handling. Code formatting. Don't use *_direct versions to raiseths2007-04-052-92/+131
* 64bit MIPS FPUs have 32 registers.ths2007-04-051-2/+1
* Fix code formatting.ths2007-04-041-66/+66
* MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registersths2007-04-021-2/+9
* Build fix for 64bit machines. (This is still not correct mul/div handling.)ths2007-04-021-6/+12
* Actually enable 64bit configuration.ths2007-04-018-38/+35
* MIPS64 configurations.ths2007-04-011-2/+0
* Malta CBUS UART support.ths2007-03-311-1/+1
* Update mips TODO.ths2007-03-301-5/+1
* Fix typo, suggested by Ben Taylor.ths2007-03-301-1/+1
* Squash logic bugs while they are fresh...ths2007-03-301-1/+0
* Sanitize mips exception handling.ths2007-03-305-73/+55
* One more bit of mips CPU configuration, and support for early 4KEcths2007-03-241-1/+23
* Fix enough FPU/R2 support to get 24Kf going.ths2007-03-235-26/+66
* Move mips CPU specific initialization to translate_init.c.ths2007-03-213-40/+61
* Barf on branches/jumps in branch delay slots. Spotted by Stefan Weil.ths2007-03-191-5/+13
* Define gen_intermediate_code_internal as "static inline".ths2007-03-191-2/+3
* SPARC host fixes, by Ben Taylor.ths2007-03-191-10/+0
* Fix BD flag handling, cause register contents, implement some more bitsths2007-03-182-4/+17
* MIPS -cpu selection support, by Herve Poussineau.ths2007-03-184-33/+104
* Note FPU enable/disable issue.ths2007-03-171-0/+2
* MIPS Userland TLS register emulation, by Daniel Jacobowitz.ths2007-03-023-0/+17
* MIPS FPU dynamic activation, part 1, by Herve Poussineau.ths2007-02-287-101/+65
* Fix mips FPU emulation, 32 bit data types are allowed to use odd registers.ths2007-02-272-30/+17
* Replace TLSZ with TARGET_FMT_lx.ths2007-02-205-43/+36
* Fix sign-extension of VPN field in TLB, by Herve Poussineau.ths2007-02-183-3/+3
* Update MIPS TODO.ths2007-02-021-4/+2
* Sparc arm/mips/sparc register patch, by Martin Bochnig.ths2007-02-021-0/+10
* EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.ths2007-01-243-21/+6
* Reworking MIPS interrupt handling, by Aurelien Jarno.ths2007-01-244-51/+18
* Implementing dmfc/dmtc.ths2007-01-234-86/+1434
* Update TODO.ths2007-01-221-3/+4
* Fix PageMask handling, second part.ths2007-01-223-16/+36
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