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* | target-mips: keep softfloat exception set to 0 between instructionsAurelien Jarno2012-10-311-63/+10
| | | | | | | | | | | | | | | | | | Instead of clearing the softfloat exception flags before each floating point instruction, reset them to 0 in update_fcr31() when an exception is detected. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: use the softfloat floatXX_muladd functionsAurelien Jarno2012-10-313-105/+64
| | | | | | | | | | | | | | | | | | | | Use the new softfloat floatXX_muladd() functions to implement the madd, msub, nmadd and nmsub instructions. At the same time replace the name of the helpers by the name of the instruction, as the only reason for the previous names was to keep the macros simple. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: do not save CPU state when using retranslationAurelien Jarno2012-10-311-20/+0
| | | | | | | | | | | | | | | | When the CPU state after a possible retranslation is going to be handled through code retranslation, we don't need to save the CPU state before. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: correctly restore btarget upon exceptionAurelien Jarno2012-10-311-0/+11
| | | | | | | | | | | | | | | | When the CPU state is restored through retranslation after an exception, btarget should also be restored. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: remove #if defined(TARGET_MIPS64) in opcode enumsAurelien Jarno2012-10-311-36/+0
| | | | | | | | | | | | | | | | All switch() decoding instruction have a default entry, so it is possible to have unused enum entries. Remove conditional definitions of MIPS64 opcode enums, as it only makes the code less readable. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: Change TODO fileJia Liu2012-10-311-2/+1
| | | | | | | | | | | | | | Change DSP r1 & DSP r2 into microMIPS DSP encodings in TODO file. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: Add ASE DSP processorsJia Liu2012-10-311-0/+52
| | | | | | | | | | | | | | Add 74kf and mips64dspr2-generic-cpu model for test. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: Add ASE DSP accumulator instructionsJia Liu2012-10-313-0/+995
| | | | | | | | | | | | | | Add MIPS ASE DSP Accumulator and DSPControl Access instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: Add ASE DSP compare-pick instructionsJia Liu2012-10-313-0/+635
| | | | | | | | | | | | | | Add MIPS ASE DSP Compare-Pick instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: Add ASE DSP bit/manipulation instructionsJia Liu2012-10-313-0/+311
| | | | | | | | | | | | | | Add MIPS ASE DSP Bit/Manipulation instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: Add ASE DSP multiply instructionsJia Liu2012-10-313-0/+1499
| | | | | | | | | | | | | | Add MIPS ASE DSP Multiply instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: Add ASE DSP GPR-based shift instructionsJia Liu2012-10-313-0/+618
| | | | | | | | | | | | | | Add MIPS ASE DSP GPR-Based Shift instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: Add ASE DSP arithmetic instructionsJia Liu2012-10-313-3/+1812
| | | | | | | | | | | | | | Add MIPS ASE DSP Arithmetic instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: Add ASE DSP load instructionsJia Liu2012-10-311-0/+88
| | | | | | | | | | | | | | Add MIPS ASE DSP Load instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: Add ASE DSP branch instructionsJia Liu2012-10-311-0/+36
| | | | | | | | | | | | | | Add MIPS ASE DSP Branch instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | Use correct acc value to index cpu_HI/cpu_LO rather than using a fix numberJia Liu2012-10-311-27/+95
| | | | | | | | | | Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: Add ASE DSP resources access checkJia Liu2012-10-313-2/+47
| | | | | | | | | | | | | | Add MIPS ASE DSP resources access check. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* | target-mips: Add ASE DSP internal functionsJia Liu2012-10-312-1/+1064
|/ | | | | | | Add internal functions using by MIPS ASE DSP instructions. Signed-off-by: Jia Liu <proljc@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Use TCG registers for the FPU.Richard Henderson2012-10-281-42/+54
| | | | | | | | | | | | With normal FP, this doesn't have much affect on the generated code, because most of the FP operations are not CONST/PURE, and so we spill registers in about the same frequency as the explicit load/stores. But with Loongson multimedia instructions, which are all integral and whose helpers are in fact CONST+PURE, this greatly improves the code. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: rename helper flagsAurelien Jarno2012-10-281-53/+53
| | | | | | | | Rename helper flags to the new ones. This is purely a mechanical change, it's possible to use better flags by looking at the helpers. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Rename target_phys_addr_t to hwaddrAvi Kivity2012-10-233-18/+18
| | | | | | | | | | | | | | | target_phys_addr_t is unwieldly, violates the C standard (_t suffixes are reserved) and its purpose doesn't match the name (most target_phys_addr_t addresses are not target specific). Replace it with a finger-friendly, standards conformant hwaddr. Outstanding patchsets can be fixed up with the command git rebase -i --exec 'find -name "*.[ch]" | xargs s/target_phys_addr_t/hwaddr/g' origin Signed-off-by: Avi Kivity <avi@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
* target-mips: Pass MIPSCPU to mips_vpe_sleep()Andreas Färber2012-10-171-3/+7
| | | | | | | Needed for moving halted field to CPUState. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Pass MIPSCPU to mips_tc_sleep()Andreas Färber2012-10-171-3/+5
| | | | | | | Needed for changing mips_vpe_sleep() argument type to MIPSCPU. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Pass MIPSCPU to mips_vpe_is_wfi()Andreas Färber2012-10-171-4/+8
| | | | | | | | | | Needed for moving halted field to CPUState. The variable name "c" is retained for MIPSCPU to leave "cpu" for CPUState. Also change return type to bool while at it. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Pass MIPSCPU to mips_tc_wake()Andreas Färber2012-10-171-3/+8
| | | | | | | Needed for changing mips_vpe_is_wfi() argument type to MIPSCPU. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Clean up other_cpu in helper_{d,e}vpe()Andreas Färber2012-10-171-14/+14
| | | | | | | | | Free the variable name "other_cpu" for later use for MIPSCPU. Fix off-by-one indentation while at it. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson2012-09-271-1/+2
| | | | | | | | | | | For all targets that currently call tcg_gen_debug_insn_start, add CPU_LOG_TB_OP_OPT to the condition that gates it. This is useful for comparing optimization dumps, when the pre-optimization dump is merely noise. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Implement Loongson Multimedia InstructionsRichard Henderson2012-09-194-4/+1180
| | | | | | | | Implements all of the COP2 instructions except for the S<cond> family of comparisons. The documentation is unclear for those. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Always evaluate debugging macro argumentsRichard Henderson2012-09-191-14/+17
| | | | | | | | this will prevent some of the compilation errors with debugging enabled from creeping back in. Signed-off-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Fix MIPS_DEBUG.Richard Henderson2012-09-191-36/+38
| | | | | | | | The macro uses the DisasContext. Pass it around as needed. Signed-off-by: Richard Henderson <rth@twiddle.net> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Set opn in gen_ldst_multiple.Richard Henderson2012-09-191-0/+6
| | | | | | | | Used by MIPS_DEBUG, when enabled. Signed-off-by: Richard Henderson <rth@twiddle.net> Acked-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: switch to AREG0 free modeBlue Swirl2012-09-155-1085/+1162
| | | | | | | | Add an explicit CPUState parameter instead of relying on AREG0 and switch to AREG0 free mode. Signed-off-by: Blue Swirl <blauwirbel@gmail.com> Acked-by: Aurelien Jarno <aurelien@aurel32.net>
* MIPS/user: Fix reset CPU state initializationMaciej W. Rozycki2012-09-083-62/+52
| | | | | | | | | | | | | | | | | | This change updates the CPU reset sequence to use a common piece of code that figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1X not being set where applicable that causes floating-point MADD family instructions (and other instructions from the MIPS IV FP subset) to trap. As compute_hflags is now shared between op_helper.c and translate.c, the function is now moved to a common header. There are no changes to this function. The problem was seen with the 24Kf MIPS32r2 processor in user emulation. The new approach prevents system and user emulation from diverging -- all the hflags state is initialized in one place now. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: allow microMIPS SWP and SDP to have RD equal to BASEEric Johnson2012-08-271-1/+9
| | | | | | | | | | The microMIPS SWP and SDP instructions do not modify GPRs. So their behavior is well defined when RD equals BASE. The MIPS Architecture Verification Programs (AVPs) check that they work as expected. This is required for AVPs to pass. Signed-off-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add privilege level check to several Cop0 instructionsEric Johnson2012-08-271-0/+9
| | | | | | | | | The MIPS Architecture Verification Programs (AVPs) check privileged instructions for the required privilege level. These changes are needed to pass the AVP suite. Signed-off-by: Eric Johnson <ericj@mips.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* mips-linux-user: Always support rdhwr.Richard Henderson2012-08-271-0/+4
| | | | | | | | | | The kernel will emulate this instruction if it's not supported natively. This insn is used for TLS, among other things, and so is required by modern glibc. Signed-off-by: Richard Henderson <rth@twiddle.net> Cc: Riku Voipio <riku.voipio@iki.fi> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Streamline indexed cp1 memory addressing.Richard Henderson2012-08-271-2/+1
| | | | | | We've already eliminated both base and index being zero. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Fix order of CVT.PS.S operandsRichard Sandiford2012-08-271-1/+1
| | | | | | | | | The FS input to CVT.PS.S is the high half and FT is the low half. tcg_gen_concat_i32_i64 takes the low half first, so the operands were in the wrong order. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Fix operands of RECIP2.S and RECIP2.PSRichard Sandiford2012-08-271-2/+2
| | | | | | | | Read the second input operand of RECIP2.S and RECIP2.PS from FT rather than FD. RECIP2.D is already correct. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Fix some helper functions (VR54xx multiplication)Stefan Weil2012-08-241-46/+29
| | | | | | | | | | | | | Commits b5dc7732e1cc2fb549e48b7b5d664f2c79628e2e and be24bb4f3007c3e07cbf1934f7e781493d876ab7 optimized the code and removed the correct setting of t0. Fix this. gcc-4.7 detected this bug because parameter arg1 was unused but set in set_HIT0_LO and set_HI_LOT0. Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Enable access to required RDHWR hardware registersMeador Inge2012-08-231-2/+3
| | | | | | | | | | | | | | | | | While running in the usermode emulator all of the required* MIPS32r2 RDHWR hardware registers should be accessible (the Linux kernel enables access to these same registers). Note that these registers are still enabled when the MIPS ISA is not release 2. This is OK since the Linux kernel emulates access to them when they are not available in hardware. * There is also the ULR register which is only recommended for full release 2 compliance. Incidentally, accessing this register in the current implementation works fine without flipping its access bit. Signed-off-by: Meador Inge <meadori@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* MIPS: Correct FCR0 initializationNathan Froyd2012-08-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change addresses a problem where QEMU incorrectly traps on floating-point MADD group instructions with SIGILL, at least while emulating MIPS32r2 processors. These instructions use the COP1X major opcode and include ones like: madd.d $f2,$f4,$f2,$f6 Here's Nathan's original analysis of the problem: "QEMU essentially does: d = find_cpu (cpu_string) // get CPU definition fpu_init (env, d) // initialize fpu state (init FCR0, basically) cpu_reset (env) ...and the cpu_reset call clears all interesting state that fpu_init setup, then proceeds to reinitialize all the CP0 registers...but not FCR0." I have verified this change with system emulation running the GDB test suite for the mips-sde-elf target (o32, big endian, 24Kf CPU emulated), there were 55 progressions and no regressions. Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
* build: move other target-*/ objects to nested Makefile.objsPaolo Bonzini2012-06-071-1/+2
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* build: move libobj-y variable to nested Makefile.objsPaolo Bonzini2012-06-071-1/+3
| | | | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* build: move obj-TARGET-y variables to nested Makefile.objsPaolo Bonzini2012-06-071-0/+1
| | | | | | Also drop duplicate occurrence of device-hotplug.o. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* Kill off cpu_state_reset()Andreas Färber2012-06-041-0/+3
| | | | | | | | | | | | | | | | | In commit 1bba0dc932e8826a7d030df3767daf0bc339f9a2 cpu_reset() was renamed to cpu_state_reset(), to allow introducing a new cpu_reset() that would operate on QOM objects. All callers have been updated except for one in target-mips, so drop all implementations except for the one in target-mips and move the declaration there until MIPSCPU reset can be fully QOM'ified. Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Michael Walle <michael@walle.cc> (for lm32) Acked-by: Max Filippov <jcmvbkbc@gmail.com> (for xtensa) Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> (for mb + cris) Acked-by: Alexander Graf <agraf@suse.de> (for ppc) Acked-by: Blue Swirl <blauwirbel@gmail.com>
* target-mips: Let cpu_mips_init() return MIPSCPUAndreas Färber2012-06-042-4/+12
| | | | | | | Turn cpu_init macro into a static inline function returning CPUMIPSState for backwards compatibility. Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-mips: Use cpu_reset() in do_interrupt()Andreas Färber2012-06-041-1/+2
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-mips: Use cpu_reset() in cpu_mips_init()Andreas Färber2012-06-041-1/+1
| | | | | | | | | | | | | | Commit 0f71a7095db6bc055bc5bb520d85ea650cca8a33 (target-mips: QOM'ify CPU) hooked up cpu_state_reset() to CPUClass::reset(). Dropping the introduction of subclasses for 1.1, due to mips_def_t the reset code could not be QOM'ified yet, i.e. cpu_state_reset() will not forward to CPUClass::reset(). Update cpu_mips_init() with cpu_reset() nontheless, indirectly calling cpu_state_reset(), so that generic code can be converted to call cpu_reset(). Signed-off-by: Andreas Färber <afaerber@suse.de>
* mips: Fix BC1ANY[24]F instructionsRichard Sandiford2012-05-191-4/+4
| | | | | | | | | | | | There's some dodgy application of De Morgan's law in the emulation of the MIPS BC1ANY[24]F instructions: they end up branching only if all CCs are false, rather than if one CC is. Tested on mips64-linux-gnu, where it fixes the GCC MIPS3D tests. Signed-off-by: Richard Sandiford <rdsandiford@googlemail.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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