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* Handle cpu_model in copy_cpu(), by Kirill A. Shutemov.ths2007-12-091-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3778 c046a42c-6fe2-441c-8c8c-71466251a162
* Larger physical address space for 32-bit MIPS.ths2007-12-021-0/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3765 c046a42c-6fe2-441c-8c8c-71466251a162
* Micro-optimize back-to-back store-load sequences.ths2007-11-261-103/+135
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3743 c046a42c-6fe2-441c-8c8c-71466251a162
* Optimize the conventional move operation.ths2007-11-221-0/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3720 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix off-by-one address checks in MIPS64 MMU, by Aurelien Jarno.ths2007-11-221-4/+4
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3718 c046a42c-6fe2-441c-8c8c-71466251a162
* Add older 4Km variants.ths2007-11-191-0/+34
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3708 c046a42c-6fe2-441c-8c8c-71466251a162
* Add strict checking mode for softfp code.pbrook2007-11-181-4/+4
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3688 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix MIPS64 R2 instructions.ths2007-11-183-30/+34
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3686 c046a42c-6fe2-441c-8c8c-71466251a162
* Use a valid PRid.ths2007-11-181-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3685 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix int/float inconsistencies.pbrook2007-11-173-36/+34
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3672 c046a42c-6fe2-441c-8c8c-71466251a162
* Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSPths2007-11-141-2/+19
| | | | | | | flags. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3637 c046a42c-6fe2-441c-8c8c-71466251a162
* added cpu_model parameter to cpu_init()bellard2007-11-103-29/+23
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
* Use FORCE_RET, scrap RETURN which was implemented in target-specific code.ths2007-11-095-424/+418
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3560 c046a42c-6fe2-441c-8c8c-71466251a162
* Move kernel loader parameters from the cpu state to being board specific.ths2007-11-091-5/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3557 c046a42c-6fe2-441c-8c8c-71466251a162
* Clean out the N32 macros from target-mips, and introduce MIPS ABI specificths2007-11-089-61/+61
| | | | | | | defines for linux-user. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3556 c046a42c-6fe2-441c-8c8c-71466251a162
* Formatting fix.ths2007-11-081-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3554 c046a42c-6fe2-441c-8c8c-71466251a162
* Adjust s390 addresses (the MSB is defined as "to be ignored").ths2007-10-291-1/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3486 c046a42c-6fe2-441c-8c8c-71466251a162
* Preliminary MIPS64R2 mode.ths2007-10-291-0/+21
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3479 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix logic bug which broke TLBL/TLBS handling somewhat.ths2007-10-291-3/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3478 c046a42c-6fe2-441c-8c8c-71466251a162
* Restrict CP0_PerfCnt to legal values.ths2007-10-291-1/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3476 c046a42c-6fe2-441c-8c8c-71466251a162
* Implement missing MIPS supervisor mode bits.ths2007-10-286-35/+49
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3472 c046a42c-6fe2-441c-8c8c-71466251a162
* Add sharable clz/clo inline functions and use them for the mips target.ths2007-10-273-49/+33
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3455 c046a42c-6fe2-441c-8c8c-71466251a162
* The other half of the mul64 rework. Sorry for the breakage, I committedths2007-10-261-2/+2
| | | | | | | an incomplete version of what I tested. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3454 c046a42c-6fe2-441c-8c8c-71466251a162
* Remove bogus instruction decode.ths2007-10-241-1/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3433 c046a42c-6fe2-441c-8c8c-71466251a162
* Force proper sign extension for mfc0/mfhc0 on MIPS64.ths2007-10-241-2/+2
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3432 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix writable length of the index register.ths2007-10-231-1/+8
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3431 c046a42c-6fe2-441c-8c8c-71466251a162
* Enforce proper sign extension for lwl/lwr on MIPS64.ths2007-10-231-1/+3
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3430 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix CLO calculation for MIPS64. And a small code cleanup.ths2007-10-231-5/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3428 c046a42c-6fe2-441c-8c8c-71466251a162
* Use the standard ASE check for MIPS-3D and MT.ths2007-10-233-93/+80
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3427 c046a42c-6fe2-441c-8c8c-71466251a162
* Switch bc1any* instructions off if no MIPS-3D is implemented.ths2007-10-231-1/+9
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3426 c046a42c-6fe2-441c-8c8c-71466251a162
* Handle IBE on MIPS properly.ths2007-10-202-0/+11
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3416 c046a42c-6fe2-441c-8c8c-71466251a162
* Update TODO.ths2007-10-171-0/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3402 c046a42c-6fe2-441c-8c8c-71466251a162
* Replace is_user variable with mmu_idx in softmmu core,j_mayer2007-10-144-7/+18
| | | | | | | | | | | | | | allowing support of more than 2 mmu access modes. Add backward compatibility is_user variable in targets code when needed. Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions. Implement per target mmu modes definitions. As an example, add PowerPC hypervisor mode definition and Alpha executive and kernel modes definitions. Optimize PowerPC case, precomputing mmu_idx when MSR register changes and using the same definition in code translation code. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
* Update TODO.ths2007-10-131-1/+26
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3383 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix off-by-one in address check.ths2007-10-131-11/+8
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3382 c046a42c-6fe2-441c-8c8c-71466251a162
* Unify '-cpu ?' option.j_mayer2007-10-121-0/+1
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3380 c046a42c-6fe2-441c-8c8c-71466251a162
* Use always_inline in the MIPS support where applicable.ths2007-10-094-28/+28
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3375 c046a42c-6fe2-441c-8c8c-71466251a162
* Delete file which should have been removed in the lst commit.ths2007-10-091-301/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3373 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix [ls][wd][lr] instructions, by Aurelien Jarno.ths2007-10-094-67/+206
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3372 c046a42c-6fe2-441c-8c8c-71466251a162
* Code provision for n32/n64 mips userland emulation. Not functional yet.ths2007-09-3011-66/+66
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3284 c046a42c-6fe2-441c-8c8c-71466251a162
* Update TODO.ths2007-09-301-7/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3278 c046a42c-6fe2-441c-8c8c-71466251a162
* Supervisor mode implementation, by Aurelien Jarno.ths2007-09-293-34/+46
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3267 c046a42c-6fe2-441c-8c8c-71466251a162
* Less magic constants.ths2007-09-291-25/+29
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3266 c046a42c-6fe2-441c-8c8c-71466251a162
* Fix MIPS FP underflow handling, spotted by Daniel Jacobowitz.ths2007-09-281-13/+0
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3255 c046a42c-6fe2-441c-8c8c-71466251a162
* Move get_sp_from_cpustate from cpu.h to target_signal.h.ths2007-09-271-5/+0
| | | | | | | Enable sigaltstack processing for more architectures. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3253 c046a42c-6fe2-441c-8c8c-71466251a162
* linux-user sigaltstack() syscall, by Thayne Harbaugh.ths2007-09-271-0/+5
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3252 c046a42c-6fe2-441c-8c8c-71466251a162
* hflags computation cleanup, by Aurelien Jarno.ths2007-09-263-62/+32
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3243 c046a42c-6fe2-441c-8c8c-71466251a162
* Wrap a few often used tests with unlikely(), by Aurelien Jarno.ths2007-09-261-6/+6
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3242 c046a42c-6fe2-441c-8c8c-71466251a162
* Timer start/stop implementation, by Aurelien Jarno.ths2007-09-253-3/+22
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3237 c046a42c-6fe2-441c-8c8c-71466251a162
* Optimise instructions accessing CP0, by Aurelien Jarno.ths2007-09-254-34/+49
| | | | git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3235 c046a42c-6fe2-441c-8c8c-71466251a162
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