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* target-mips: pass 0 instead of -1 as rs in microMIPS LUI instructionLeon Alrae2015-02-131-1/+1
* target-mips: fix broken snapshottingLeon Alrae2015-02-131-2/+4
* target-mips: use CP0EnLo_XI instead of magic numberLeon Alrae2015-02-131-2/+2
* target-mips: ll and lld cause AdEL exception for unaligned addressLeon Alrae2015-02-131-3/+7
* target-mips: fix detection of the end of the page during translationLeon Alrae2015-02-131-1/+4
* target-mips: Make CP0.Status.CU1 read-only for the 5Kc and 5KEc processorsMaciej W. Rozycki2015-02-131-2/+2
* tcg: Introduce tcg_op_buf_count and tcg_op_buf_fullRichard Henderson2015-02-121-5/+3
* tcg: Move emit of INDEX_op_end into gen_tb_endRichard Henderson2015-02-121-1/+1
* target-mips: Clean up switch fall through after commit fecd264Markus Armbruster2015-02-101-0/+4
* softfloat: expand out STATUS_VARPeter Maydell2015-02-061-28/+28
* softfloat: Expand out the STATUS_PARAM macroPeter Maydell2015-02-061-8/+10
* target-mips: Don't use _raw load/store accessorsPeter Maydell2015-01-201-2/+2
* exec.c: Drop TARGET_HAS_ICE define and checksPeter Maydell2015-01-201-1/+0
* kvm: extend kvm_irqchip_add_msi_route to work on s390Frank Blaschka2015-01-121-0/+6
* gen-icount: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-1/+1
* translate: check cflags instead of use_icount globalPaolo Bonzini2015-01-031-10/+14
* Merge remote-tracking branch 'remotes/lalrae/tags/mips-20141216' into stagingPeter Maydell2014-12-178-382/+616
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| * target-mips: remove excp_names[] from linux-user as it is unusedLeon Alrae2014-12-161-1/+1
| * target-mips: convert single case switch into if statementLeon Alrae2014-12-161-3/+1
| * target-mips: Fix DisasContext's ulri member initializationMaciej W. Rozycki2014-12-161-1/+1
| * target-mips: Use local float status pointer across MSA macrosMaciej W. Rozycki2014-12-161-35/+34
| * target-mips: Add missing calls to synchronise SoftFloat statusMaciej W. Rozycki2014-12-164-17/+17
| * target-mips: Also apply the CP0.Status mask to MTTC0Maciej W. Rozycki2014-12-161-1/+2
| * target-mips: gdbstub: Clean up FPU register handlingMaciej W. Rozycki2014-12-161-19/+19
| * target-mips: Correct 32-bit address space wrappingMaciej W. Rozycki2014-12-162-8/+19
| * target-mips: Tighten ISA level checksMaciej W. Rozycki2014-12-163-15/+114
| * target-mips: Fix CP0.Config3.ISAOnExc write accessesMaciej W. Rozycki2014-12-163-2/+15
| * target-mips: Output CP0.Config2-5 in the register dumpMaciej W. Rozycki2014-12-161-0/+4
| * target-mips: Fix the 64-bit case for microMIPS MOVE16 and MOVEPMaciej W. Rozycki2014-12-161-3/+3
| * target-mips: Correct the writes to Status and Cause registers via gdbstubMaciej W. Rozycki2014-12-163-86/+102
| * target-mips: Correct the handling of writes to CP0.Status for MIPSr6Maciej W. Rozycki2014-12-161-2/+4
| * target-mips: Correct MIPS16/microMIPS branch size calculationMaciej W. Rozycki2014-12-161-1/+2
| * target-mips: Restore the order of helpersMaciej W. Rozycki2014-12-161-159/+160
| * target-mips: Remove unused `FLOAT_OP' macroMaciej W. Rozycki2014-12-161-2/+0
| * target-mips: Make `helper_float_cvtw_s' consistent with the remaining helpersMaciej W. Rozycki2014-12-161-1/+1
| * target-mips: Fix formatting in `decode_opc'Maciej W. Rozycki2014-12-161-5/+8
| * target-mips: Fix formatting in `mips_defs'Maciej W. Rozycki2014-12-161-19/+21
| * target-mips: Fix formatting in `decode_extended_mips16_opc'Maciej W. Rozycki2014-12-161-1/+1
| * target-mips: Enable vectored interrupt support for the 74Kf CPUMaciej W. Rozycki2014-12-161-1/+1
| * target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processorsMaciej W. Rozycki2014-12-161-0/+41
| * target-mips: Make CP0.Config4 and CP0.Config5 registers signedMaciej W. Rozycki2014-12-161-4/+4
| * target-mips: Add 5KEc and 5KEf MIPS64r2 processorsMaciej W. Rozycki2014-12-161-0/+45
| * target-mips: Make CP1.FIR read-only here tooMaciej W. Rozycki2014-12-161-1/+1
| * target-mips: Correct the handling of register #72 on writesMaciej W. Rozycki2014-12-161-1/+1
* | qemu-log: add log category for MMU infoAntony Pavlov2014-12-161-2/+4
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* target-mips: kvm: do not use get_clock()Paolo Bonzini2014-12-151-1/+1
* target-mips: fix multiple TCG registers covering same dataYongbok Kim2014-11-071-5/+3
* mips: Ensure PC update with MTC0 single-steppingMaciej W. Rozycki2014-11-071-1/+1
* target-mips: fix for missing delay slot in BC1EQZ and BC1NEZLeon Alrae2014-11-071-0/+1
* mips: Set the CP0.Config3.DSP and CP0.Config3.DSP2P bitsMaciej W. Rozycki2014-11-071-3/+5
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