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* tcg: Change tcg_global_mem_new_* to take a TCGv_ptrRichard Henderson2019-11-291-12/+13
* log: do not unnecessarily include qom/cpu.hPaolo Bonzini2019-11-292-0/+2
* mips: Clean up includesPeter Maydell2019-11-2911-9/+11
* target-mips: Fix ALIGN instruction when bp=0Miodrag Dinic2019-11-291-1/+10
* target-mips: silence NaNs for cvt.s.d and cvt.d.sAurelien Jarno2019-11-291-0/+2
* target-mips/cpu.h: Fix spell errorDongxue Zhang2019-11-291-1/+1
* fpu: Replace int32 typedef with int32_tPeter Maydell2019-11-291-12/+12
* fpu: Replace uint64 typedef with uint64_tPeter Maydell2019-11-291-2/+2
* fpu: Replace int64 typedef with int64_tPeter Maydell2019-11-291-6/+6
* target-mips: flush QEMU TLB when disabling 64-bit addressingLeon Alrae2015-11-242-14/+17
* target-mips: Fix exceptions while UX=0James Hogan2015-11-241-0/+12
* target-mips: fix updating XContext on mmu exceptionYongbok Kim2015-10-301-3/+4
* target-mips: add SIGRIE instructionYongbok Kim2015-10-301-1/+11
* target-mips: Set Config5.XNP for R6 coresYongbok Kim2015-10-301-2/+2
* target-mips: add PC, XNP reg numbers to RDHWRYongbok Kim2015-10-304-32/+63
* target-mips: Add enum for BREAK32Yongbok Kim2015-10-291-1/+2
* target-mips: update writing to CP0.Status.KX/SX/UX in MIPS Release R6Leon Alrae2015-10-291-1/+6
* target-mips: implement the CPU wake-up on non-enabled interrupts in R6Leon Alrae2015-10-291-3/+4
* target-mips: move the test for enabled interrupts to a separate functionLeon Alrae2015-10-293-16/+20
* target-*: Advance pc after recognizing a breakpointRichard Henderson2015-10-281-2/+4
* disas: QOMify mips specific disas setupPeter Crosthwaite2015-10-221-0/+9
* kvm: Pass PCI device pointer to MSI routing functionsPavel Fedin2015-10-191-1/+1
* qdev: Protect device-list-properties against broken devicesMarkus Armbruster2015-10-091-0/+7
* tcg: Remove gen_intermediate_code_pcRichard Henderson2015-10-071-43/+5
* tcg: Pass data argument to restore_state_to_opcRichard Henderson2015-10-071-4/+5
* tcg: Add TCG_MAX_INSNSRichard Henderson2015-10-071-1/+6
* target-*: Drop cpu_gen_code defineRichard Henderson2015-10-071-1/+0
* target-mips: Add delayed branch state to insn_startRichard Henderson2015-10-072-1/+3
* target-*: Introduce and use cpu_breakpoint_testRichard Henderson2015-10-071-15/+10
* target-*: Increment num_insns immediately after tcg_gen_insn_startRichard Henderson2015-10-071-3/+2
* target-*: Unconditionally emit tcg_gen_insn_startRichard Henderson2015-10-071-5/+4
* tcg: Rename debug_insn_start to insn_startRichard Henderson2015-10-071-1/+1
* mips: Remove ELF_MACHINE from cpu.hPeter Crosthwaite2015-09-251-2/+0
* target-mips: improve exception handlingPavel Dovgaluk2015-09-185-377/+425
* target-mips: correct MTC0 instruction on MIPS64Leon Alrae2015-09-181-11/+7
* target-mips: add missing restriction in DAUI instructionLeon Alrae2015-09-181-1/+3
* target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONSAurelien Jarno2015-09-181-39/+0
* target-mips: get rid of MIPS_DEBUGAurelien Jarno2015-09-181-605/+19
* target-mips: Fix RDHWR on CP0.CountAlex Smith2015-09-181-2/+7
* target-mips: remove wrong checks for recip.fmt and rsqrt.fmtPetar Jovanovic2015-09-181-4/+2
* target-mips: Use tcg_gen_extrh_i64_i32Richard Henderson2015-09-181-26/+22
* tlb: Add "ifetch" argument to cpu_mmu_index()Benjamin Herrenschmidt2015-09-112-3/+3
* typofixes - v4Veres Lajos2015-09-111-1/+1
* maint: remove unused include for signal.hDaniel P. Berrange2015-09-111-1/+0
* tcg: Remove tcg_gen_trunc_i64_i32Richard Henderson2015-08-241-2/+2
* target-mips: Use CPU_LOG_INT for logging related to interruptsRichard Henderson2015-08-132-20/+13
* target-mips: simplify LWL/LDL mask generationAurelien Jarno2015-08-131-8/+6
* target-mips: update mips32r5-generic into P5600Yongbok Kim2015-08-132-25/+30
* target-mips: Copy restrictions from ext/ins to dext/dinsRichard Henderson2015-08-041-20/+25
* target-mips: fix semihosting for microMIPS R6Leon Alrae2015-08-041-3/+7
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