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* MIPS32R2 needs RDPGPR/WRPGPR instructions even when no shadow registersths2007-04-021-2/+9
* Build fix for 64bit machines. (This is still not correct mul/div handling.)ths2007-04-021-6/+12
* Actually enable 64bit configuration.ths2007-04-018-38/+35
* MIPS64 configurations.ths2007-04-011-2/+0
* Malta CBUS UART support.ths2007-03-311-1/+1
* Update mips TODO.ths2007-03-301-5/+1
* Fix typo, suggested by Ben Taylor.ths2007-03-301-1/+1
* Squash logic bugs while they are fresh...ths2007-03-301-1/+0
* Sanitize mips exception handling.ths2007-03-305-73/+55
* One more bit of mips CPU configuration, and support for early 4KEcths2007-03-241-1/+23
* Fix enough FPU/R2 support to get 24Kf going.ths2007-03-235-26/+66
* Move mips CPU specific initialization to translate_init.c.ths2007-03-213-40/+61
* Barf on branches/jumps in branch delay slots. Spotted by Stefan Weil.ths2007-03-191-5/+13
* Define gen_intermediate_code_internal as "static inline".ths2007-03-191-2/+3
* SPARC host fixes, by Ben Taylor.ths2007-03-191-10/+0
* Fix BD flag handling, cause register contents, implement some more bitsths2007-03-182-4/+17
* MIPS -cpu selection support, by Herve Poussineau.ths2007-03-184-33/+104
* Note FPU enable/disable issue.ths2007-03-171-0/+2
* MIPS Userland TLS register emulation, by Daniel Jacobowitz.ths2007-03-023-0/+17
* MIPS FPU dynamic activation, part 1, by Herve Poussineau.ths2007-02-287-101/+65
* Fix mips FPU emulation, 32 bit data types are allowed to use odd registers.ths2007-02-272-30/+17
* Replace TLSZ with TARGET_FMT_lx.ths2007-02-205-43/+36
* Fix sign-extension of VPN field in TLB, by Herve Poussineau.ths2007-02-183-3/+3
* Update MIPS TODO.ths2007-02-021-4/+2
* Sparc arm/mips/sparc register patch, by Martin Bochnig.ths2007-02-021-0/+10
* EBase is limited to KSEG0/KSEG1 even on 64bit CPUs.ths2007-01-243-21/+6
* Reworking MIPS interrupt handling, by Aurelien Jarno.ths2007-01-244-51/+18
* Implementing dmfc/dmtc.ths2007-01-234-86/+1434
* Update TODO.ths2007-01-221-3/+4
* Fix PageMask handling, second part.ths2007-01-223-16/+36
* TLB address wraparound hopefully fixed now.ths2007-01-211-1/+0
* Bring TLB / PageSize handling in line with real hardware behaviour.ths2007-01-212-25/+5
* Note more issues.ths2007-01-191-6/+17
* Keep track of mips related issues.ths2007-01-171-0/+17
* moved invalidate_tlb() to helper.c as a work around for gcc 3.2.2 bug - suppr...bellard2007-01-033-45/+45
* Fix bad data type.ths2007-01-011-1/+1
* Fix lwl/lwr for 64bit emulation, also debug output spec for 64bit emulation.ths2007-01-011-24/+26
* Simplify code and fix formatting.ths2007-01-011-6/+6
* Check ELF binaries for machine type and endianness.ths2006-12-231-0/+2
* Use memory barriers in FORCE_RET / RETURN.ths2006-12-231-2/+2
* Scrap SIGN_EXTEND32.ths2006-12-215-74/+71
* Preliminiary MIPS64 support, disabled by default due to performance impact.ths2006-12-2111-202/+949
* Fix erraneous fallthrough in MIPS trap implementation, thanks Atsushi Nemoto.ths2006-12-161-0/+1
* Handle invalid accesses as SIGILL for mips/mipsel userland emulation.ths2006-12-102-0/+10
* Fix build of MIPS target without FPU support.ths2006-12-072-0/+26
* Fix reset handling, CP0 isn't enabled by default (a fact which doesn'tths2006-12-072-38/+31
* Simplify mask construction.ths2006-12-071-2/+2
* Update copyright notice.ths2006-12-061-0/+1
* Add MIPS32R2 instructions, and generally straighten out the instructionths2006-12-067-591/+2235
* Dynamically translate MIPS mtc0 instructions.ths2006-12-064-220/+423
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