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* remove target ifdefs from vl.caurel322008-05-041-0/+22
* Simplify mips branch handling. Retire T2 from use. Use TCG for branches.ths2008-05-045-77/+55
* Fix MIPS MT GPR accesses, thanks Stefan Weil.ths2008-05-032-10/+10
* Factorize code in translate.caurel322008-04-281-0/+8
* Remove osdep.c/qemu-img code duplicationaurel322008-04-111-0/+1
* Fix infinite loop when invalidating TLB, by Herve Poussineau.ths2008-03-291-1/+1
* Make MIPS MT implementation more cache friendly.ths2008-02-125-59/+59
* use the TCG code generatorbellard2008-02-012-55/+6
* Fix typo which broke MIPS32R2 64-bit FPU support.ths2008-01-091-1/+1
* Fix broken absoluteness check for cabs.d.*.ths2008-01-081-2/+2
* Handle some more exception types.ths2008-01-041-29/+43
* Fix exception debug output.ths2008-01-031-39/+36
* MIPS COP1X (and related) instructions, by Richard Sandiford.ths2007-12-303-18/+74
* Set FCR0.F64 for MIPS64R2-generic, by Richard Sandiford.ths2007-12-281-3/+3
* De-cruft exception definitions, and implement nicer debug output.ths2007-12-262-26/+65
* Support for VR5432, and some of its special instructions. Original patchths2007-12-256-7/+405
* 5K and 20K are Release 1 CPUs.ths2007-12-251-3/+3
* Avoid host FPE for overflowing division on MIPS, by Richard Sandiford.ths2007-12-251-3/+10
* Improved PABITS handling, and config register fixes.ths2007-12-254-56/+106
* Update debug code to match new accumulator register layout.ths2007-12-241-4/+4
* Fix CCRes value for 20Kc.ths2007-12-241-1/+1
* MIPS TODO: mention unimplemented system controllers.ths2007-12-171-0/+2
* Update MIPS TODO. The mipsnet failure is caused by a kernel bug.ths2007-12-171-6/+0
* Handle cpu_model in copy_cpu(), by Kirill A. Shutemov.ths2007-12-091-0/+1
* Larger physical address space for 32-bit MIPS.ths2007-12-021-0/+3
* Micro-optimize back-to-back store-load sequences.ths2007-11-261-103/+135
* Optimize the conventional move operation.ths2007-11-221-0/+6
* Fix off-by-one address checks in MIPS64 MMU, by Aurelien Jarno.ths2007-11-221-4/+4
* Add older 4Km variants.ths2007-11-191-0/+34
* Add strict checking mode for softfp code.pbrook2007-11-181-4/+4
* Fix MIPS64 R2 instructions.ths2007-11-183-30/+34
* Use a valid PRid.ths2007-11-181-1/+1
* Fix int/float inconsistencies.pbrook2007-11-173-36/+34
* Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSPths2007-11-141-2/+19
* added cpu_model parameter to cpu_init()bellard2007-11-103-29/+23
* Use FORCE_RET, scrap RETURN which was implemented in target-specific code.ths2007-11-095-424/+418
* Move kernel loader parameters from the cpu state to being board specific.ths2007-11-091-5/+0
* Clean out the N32 macros from target-mips, and introduce MIPS ABI specificths2007-11-089-61/+61
* Formatting fix.ths2007-11-081-1/+1
* Adjust s390 addresses (the MSB is defined as "to be ignored").ths2007-10-291-1/+5
* Preliminary MIPS64R2 mode.ths2007-10-291-0/+21
* Fix logic bug which broke TLBL/TLBS handling somewhat.ths2007-10-291-3/+3
* Restrict CP0_PerfCnt to legal values.ths2007-10-291-1/+1
* Implement missing MIPS supervisor mode bits.ths2007-10-286-35/+49
* Add sharable clz/clo inline functions and use them for the mips target.ths2007-10-273-49/+33
* The other half of the mul64 rework. Sorry for the breakage, I committedths2007-10-261-2/+2
* Remove bogus instruction decode.ths2007-10-241-1/+0
* Force proper sign extension for mfc0/mfhc0 on MIPS64.ths2007-10-241-2/+2
* Fix writable length of the index register.ths2007-10-231-1/+8
* Enforce proper sign extension for lwl/lwr on MIPS64.ths2007-10-231-1/+3
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