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* MIPS TLB style selection at runtime, by Herve Poussineau.ths2007-05-138-114/+149
* Implemented cabs FP instructions, and improve exception handling forths2007-05-112-40/+180
* Another bit of nicer debug output.ths2007-05-111-1/+1
* Implement FP madd/msub, wire up bc1any[24][ft].ths2007-05-112-12/+140
* Improved debug output for the MIPS opcode decoder.ths2007-05-111-85/+77
* Fix missing status ro mask initialization, thanks Stefan Weil.ths2007-05-111-0/+1
* Fix for the scd instruction, by Aurelien Jarno.ths2007-05-101-0/+1
* Preliminary MIPS 64-bit MMU implementation, by Aurelien Jarno.ths2007-05-091-5/+57
* Fix MIPS64 address computation specialcase, by Aurelien Jarno.ths2007-05-092-2/+18
* Work around gcc's mips define, spotted by Stefan Weil.ths2007-05-081-12/+12
* MIPS 64-bit FPU support, plus some collateral bugfixes in theths2007-05-079-518/+1700
* Update TODO.ths2007-05-071-4/+3
* Clear BD slot on next exception if appropriate.ths2007-05-071-0/+4
* Fix a really stupid bug in the [ls]d[lr] emulation, by Herve Poussineau.ths2007-05-051-3/+3
* Kill broken host register definitions, thanks to Paul Brook and Herveths2007-04-292-13/+4
* Revert last checkin.ths2007-04-291-1/+1
* Hopefully the final fix for LUI sign extensions.ths2007-04-291-1/+1
* Update TODO.ths2007-04-281-0/+9
* Next attempt to get the lui sign extension right.ths2007-04-252-3/+2
* Fix lui sign extension.ths2007-04-251-1/+1
* Update comment. We can't easily adhere to the architecture spec becauseths2007-04-191-3/+3
* Choose number of TLBs at runtime, by Herve Poussineau.ths2007-04-176-26/+25
* Simplify branch likely handling.ths2007-04-161-6/+8
* Don't use T2 for INS, it conflicts with branch delay slot handling.ths2007-04-152-6/+6
* Fix qemu SIGFPE caused by division-by-zero due to underflow.ths2007-04-153-13/+28
* Small code generation optimization.ths2007-04-151-3/+6
* Delete unused define.ths2007-04-151-2/+0
* Restart interrupts after an exception.ths2007-04-142-9/+33
* Nicer Log formatting.ths2007-04-131-1/+1
* Another fix for CP0 Cause register handling.ths2007-04-132-2/+2
* Make SYNCI_Step and CCRes CPU-specific.ths2007-04-112-3/+16
* Throw RI for invalid MFMC0-class instructions. Introduce optionalths2007-04-112-3/+18
* Code formatting fix.ths2007-04-111-935/+938
* More Context/Xcontext fixes. Ifdef some 64bit-only ops, they mayths2007-04-112-10/+10
* Fix CP0_IntCtl handling.ths2007-04-092-2/+6
* Proper handling of reserved bits in the context register.ths2007-04-091-1/+1
* Mark watchpoint features as unimplemented.ths2007-04-092-3/+9
* Catch unaligned sc/scd.ths2007-04-092-0/+10
* Fix exception handling cornercase for rdhwr.ths2007-04-092-37/+9
* Remove bogus mtc0 handling.ths2007-04-091-10/+0
* Unify IRQ handling.pbrook2007-04-071-0/+2
* cpu_get_phys_page_debug should return target_phys_addr_tj_mayer2007-04-071-2/+2
* Implement prefx.ths2007-04-071-1/+41
* Set proper BadVAddress value for unaligned instruction fetch.ths2007-04-071-1/+2
* Actually skip over delay slot for a non-taken branch likely.ths2007-04-071-2/+2
* Fix ins/ext cornercase.ths2007-04-071-4/+4
* Fix handling of ADES exceptions.ths2007-04-061-1/+3
* Save state for all CP0 instructions, they may throw a CPU exception.ths2007-04-063-16/+45
* fix branch delay slot cornercases.ths2007-04-052-3/+6
* Fix rotr immediate ops, mask shift/rotate arguments to their allowedths2007-04-053-48/+103
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