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* target-mips/translate.c: Free TCG in OPC_DINSVDongxue Zhang2014-07-281-0/+3
* mips/kvm: Disable FPU on reset with KVMJames Hogan2014-07-091-0/+7
* mips/kvm: Init EBase to correct KSEG0James Hogan2014-07-051-1/+7
* target-mips: copy CP0_Config1 into DisasContextAurelien Jarno2014-06-201-9/+11
* Merge remote-tracking branch 'remotes/kvm/uq/master' into stagingPeter Maydell2014-06-206-13/+758
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| * target-mips: Enable KVM support in build systemSanjay Lal2014-06-181-0/+1
| * target-mips: Call kvm_mips_reset_vcpu() from mips_cpu_reset()James Hogan2014-06-181-0/+8
| * target-mips: kvm: Add main KVM support for MIPSSanjay Lal2014-06-182-0/+709
| * target-mips: get_physical_address: Add KVM awarenessJames Hogan2014-06-181-7/+26
| * target-mips: get_physical_address: Add defines for segment basesJames Hogan2014-06-181-6/+12
| * target-mips: Reset CPU timer consistentlyJames Hogan2014-06-181-0/+2
* | target-mips: implement UserLocal RegisterPetar Jovanovic2014-06-184-13/+83
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* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-052-5/+2
* softmmu: commonize helper definitionsPaolo Bonzini2014-06-051-14/+0
* softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini2014-06-052-1/+1
* softmmu: make do_unaligned_access a method of CPUPaolo Bonzini2014-06-053-6/+8
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-285-12/+5
* target-mips: Avoid shifting left into sign bitPeter Maydell2014-03-274-17/+17
* target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 modePetar Jovanovic2014-03-251-35/+44
* cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber2014-03-131-1/+1
* cputlb: Change tlb_flush() argument to CPUStateAndreas Färber2014-03-133-3/+6
* cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber2014-03-131-2/+6
* exec: Change cpu_abort() argument to CPUStateAndreas Färber2014-03-132-3/+12
* translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber2014-03-131-1/+1
* cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber2014-03-131-2/+2
* exec: Change tlb_fill() argument to CPUStateAndreas Färber2014-03-131-3/+4
* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-133-3/+4
* cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber2014-03-133-20/+24
* cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber2014-03-134-11/+16
* cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2014-03-132-28/+30
* target-mips: add user-mode FR switch support for MIPS32r5Petar Jovanovic2014-02-104-10/+56
* target-mips: add support for CP0_Config5Petar Jovanovic2014-02-105-3/+40
* target-mips: add support for CP0_Config4Petar Jovanovic2014-02-105-3/+31
* target-mips: add CPU definition for MIPS32R5Petar Jovanovic2014-02-102-0/+33
* target-mips: Use new qemu_ld/st opcodesAurelien Jarno2013-12-211-67/+52
* target-mips: Use macro ARRAY_SIZE where possibleStefan Weil2013-12-091-18/+12
* target-mips: fix 64-bit FPU config for user-mode emulationPetar Jovanovic2013-12-091-2/+5
* misc: Replace 'struct QEMUTimer' by 'QEMUTimer'Stefan Weil2013-12-021-1/+1
* Merge remote-tracking branch 'rth/tcg-pull' into stagingAnthony Liguori2013-10-112-10/+6
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| * tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson2013-10-101-6/+6
| * tcg: Move helper registration into tcg_context_initRichard Henderson2013-10-101-4/+0
* | cpu: Drop cpu_model_str from CPU_COMMONAndreas Färber2013-10-071-1/+0
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* cpu: Use QTAILQ for CPU listAndreas Färber2013-09-031-6/+4
* tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson2013-09-021-1/+1
* target-mips: fix get_physical_address() #if 0 build errorJames Hogan2013-08-281-1/+1
* target-mips: fix decoding of microMIPS POOL32Axf instructionsLeon Alrae2013-08-061-6/+54
* target-mips: fix 34Kf configuration for DSP ASEYongbok Kim2013-08-031-4/+3
* cpu: Partially revert "cpu: Change qemu_init_vcpu() argument to CPUState"Andreas Färber2013-07-291-2/+3
* target-mips: fix mipsdsp_mul_q31_q31Petar Jovanovic2013-07-291-1/+1
* target-mips: Remove assignment to a variable which is never usedStefan Weil2013-07-291-1/+0
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