summaryrefslogtreecommitdiffstats
path: root/target-mips
Commit message (Expand)AuthorAgeFilesLines
* MIPS/user: Fix reset CPU state initializationMaciej W. Rozycki2012-09-083-62/+52
* target-mips: allow microMIPS SWP and SDP to have RD equal to BASEEric Johnson2012-08-271-1/+9
* target-mips: add privilege level check to several Cop0 instructionsEric Johnson2012-08-271-0/+9
* mips-linux-user: Always support rdhwr.Richard Henderson2012-08-271-0/+4
* target-mips: Streamline indexed cp1 memory addressing.Richard Henderson2012-08-271-2/+1
* Fix order of CVT.PS.S operandsRichard Sandiford2012-08-271-1/+1
* Fix operands of RECIP2.S and RECIP2.PSRichard Sandiford2012-08-271-2/+2
* target-mips: Fix some helper functions (VR54xx multiplication)Stefan Weil2012-08-241-46/+29
* target-mips: Enable access to required RDHWR hardware registersMeador Inge2012-08-231-2/+3
* MIPS: Correct FCR0 initializationNathan Froyd2012-08-091-0/+1
* build: move other target-*/ objects to nested Makefile.objsPaolo Bonzini2012-06-071-1/+2
* build: move libobj-y variable to nested Makefile.objsPaolo Bonzini2012-06-071-1/+3
* build: move obj-TARGET-y variables to nested Makefile.objsPaolo Bonzini2012-06-071-0/+1
* Kill off cpu_state_reset()Andreas Färber2012-06-041-0/+3
* target-mips: Let cpu_mips_init() return MIPSCPUAndreas Färber2012-06-042-4/+12
* target-mips: Use cpu_reset() in do_interrupt()Andreas Färber2012-06-041-1/+2
* target-mips: Use cpu_reset() in cpu_mips_init()Andreas Färber2012-06-041-1/+1
* mips: Fix BC1ANY[24]F instructionsRichard Sandiford2012-05-191-4/+4
* target-mips: Remove commented-out function declarationAndreas Färber2012-05-121-1/+0
* target-mips: Remove unused inline functionStefan Weil2012-05-031-6/+0
* Merge branch 'qom-cpu-rest.v1' of git://github.com/afaerber/qemu-cpuBlue Swirl2012-05-014-2/+148
|\
| * target-mips: Start QOM'ifying CPU initAndreas Färber2012-04-302-1/+9
| * target-mips: QOM'ify CPUAndreas Färber2012-04-304-1/+139
* | target-mips: Move definition of uint_fast{8, 16}_t to osdep.hAndreas Färber2012-04-281-7/+0
|/
* target-mips: Fix type cast for w64 (uintptr_t)Stefan Weil2012-04-151-1/+1
* Use uintptr_t for various op related functionsBlue Swirl2012-04-141-10/+8
* Replace Qemu by QEMU in commentsStefan Weil2012-04-071-1/+1
* Replace Qemu by QEMU in internal documentationStefan Weil2012-04-071-2/+2
* target-mips: Add compiler attribute to some functions which don't returnStefan Weil2012-03-242-3/+4
* Rename CPUState -> CPUArchStateAndreas Färber2012-03-141-1/+1
* target-mips: Don't overuse CPUStateAndreas Färber2012-03-145-274/+274
* Rename cpu_reset() to cpu_state_reset()Andreas Färber2012-03-142-3/+3
* Spelling fixes in comments (it's -> its)Stefan Weil2012-03-081-1/+1
* target-mips: Clean includesStefan Weil2012-02-281-7/+0
* Fix spelling in comments, documentation and messagesStefan Weil2011-12-141-1/+1
* fix spelling in target sub directoryDong Xu Wang2011-12-022-2/+2
* softmmu_header: pass CPUState to tlb_fillBlue Swirl2011-10-011-4/+3
* mips: Support the MT TCStatus IXMT irq disable flagEdgar E. Iglesias2011-09-061-0/+4
* mips: Add MT halting and waking of VPEsEdgar E. Iglesias2011-09-062-4/+129
* mips: Initialize MT state at resetEdgar E. Iglesias2011-09-061-0/+26
* mips: Default to using one VPE and one TC.Edgar E. Iglesias2011-09-061-1/+1
* mips: Enable VInt interrupt mode for the 34KfEdgar E. Iglesias2011-09-061-1/+1
* mips: Correct VInt vector generationEdgar E. Iglesias2011-09-061-3/+3
* mips: Correct IntCtl write mask for VIntEdgar E. Iglesias2011-09-061-1/+1
* mips: Hook in more reg accesses via mttr/mftrEdgar E. Iglesias2011-09-063-11/+225
* mips: Synchronize CP0 TCSTatus, Status and EntryHiEdgar E. Iglesias2011-09-061-44/+106
* mips: Handle TC indexing of other VPEsEdgar E. Iglesias2011-09-061-105/+161
* Use glib memory allocation and free functionsAnthony Liguori2011-08-202-3/+3
* Remove unused is_softmmu parameter from cpu_handle_mmu_faultBlue Swirl2011-08-073-5/+5
* exec.h cleanupBlue Swirl2011-07-303-61/+57
OpenPOWER on IntegriCloud