summaryrefslogtreecommitdiffstats
path: root/target-mips
Commit message (Expand)AuthorAgeFilesLines
...
* target-mips: fix wrong microMIPS opcode encoding陳韋任 (Wei-Ren Chen)2012-11-151-1/+1
* target-mips: Fix seg fault for LUI when MIPS_DEBUG_DISAS==1.Eric Johnson2012-11-111-7/+11
* disas: avoid using cpu_single_envBlue Swirl2012-11-101-1/+1
* target-mips: use ULL for 64 bit constantsBlue Swirl2012-11-051-2/+2
* Merge remote-tracking branch 'afaerber/qom-cpu' into stagingAnthony Liguori2012-11-011-5/+6
|\
| * cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber2012-10-311-5/+6
* | target-mips: don't flush extra TLB on permissions upgradeAurelien Jarno2012-10-311-5/+23
* | target-mips: fix TLBR wrt SEGMaskAurelien Jarno2012-10-311-0/+6
* | target-mips: use deposit instead of hardcoded versionAurelien Jarno2012-10-311-28/+4
* | target-mips: optimize ddiv/ddivu/div/divu with movcondAurelien Jarno2012-10-311-48/+37
* | target-mips: implement movn/movz using movcondAurelien Jarno2012-10-311-15/+12
* | target-mips: don't use local temps for store conditionalAurelien Jarno2012-10-311-5/+6
* | target-mips: implement unaligned loads using TCGAurelien Jarno2012-10-313-159/+62
* | target-mips: simplify load/store microMIPS helpersAurelien Jarno2012-10-311-64/+9
* | target-mips: optimize load operationsAurelien Jarno2012-10-311-4/+12
* | target-mips: cleanup load/store operationsAurelien Jarno2012-10-311-64/+35
* | target-mips: restore CPU state after an FPU exceptionAurelien Jarno2012-10-311-90/+95
* | target-mips: use softfloat constants when possibleAurelien Jarno2012-10-311-48/+44
* | target-mips: cleanup float to int conversion helpersAurelien Jarno2012-10-311-39/+79
* | target-mips: fix FPU exceptionsAurelien Jarno2012-10-311-13/+19
* | target-mips: keep softfloat exception set to 0 between instructionsAurelien Jarno2012-10-311-63/+10
* | target-mips: use the softfloat floatXX_muladd functionsAurelien Jarno2012-10-313-105/+64
* | target-mips: do not save CPU state when using retranslationAurelien Jarno2012-10-311-20/+0
* | target-mips: correctly restore btarget upon exceptionAurelien Jarno2012-10-311-0/+11
* | target-mips: remove #if defined(TARGET_MIPS64) in opcode enumsAurelien Jarno2012-10-311-36/+0
* | target-mips: Change TODO fileJia Liu2012-10-311-2/+1
* | target-mips: Add ASE DSP processorsJia Liu2012-10-311-0/+52
* | target-mips: Add ASE DSP accumulator instructionsJia Liu2012-10-313-0/+995
* | target-mips: Add ASE DSP compare-pick instructionsJia Liu2012-10-313-0/+635
* | target-mips: Add ASE DSP bit/manipulation instructionsJia Liu2012-10-313-0/+311
* | target-mips: Add ASE DSP multiply instructionsJia Liu2012-10-313-0/+1499
* | target-mips: Add ASE DSP GPR-based shift instructionsJia Liu2012-10-313-0/+618
* | target-mips: Add ASE DSP arithmetic instructionsJia Liu2012-10-313-3/+1812
* | target-mips: Add ASE DSP load instructionsJia Liu2012-10-311-0/+88
* | target-mips: Add ASE DSP branch instructionsJia Liu2012-10-311-0/+36
* | Use correct acc value to index cpu_HI/cpu_LO rather than using a fix numberJia Liu2012-10-311-27/+95
* | target-mips: Add ASE DSP resources access checkJia Liu2012-10-313-2/+47
* | target-mips: Add ASE DSP internal functionsJia Liu2012-10-312-1/+1064
|/
* target-mips: Use TCG registers for the FPU.Richard Henderson2012-10-281-42/+54
* target-mips: rename helper flagsAurelien Jarno2012-10-281-53/+53
* Rename target_phys_addr_t to hwaddrAvi Kivity2012-10-233-18/+18
* target-mips: Pass MIPSCPU to mips_vpe_sleep()Andreas Färber2012-10-171-3/+7
* target-mips: Pass MIPSCPU to mips_tc_sleep()Andreas Färber2012-10-171-3/+5
* target-mips: Pass MIPSCPU to mips_vpe_is_wfi()Andreas Färber2012-10-171-4/+8
* target-mips: Pass MIPSCPU to mips_tc_wake()Andreas Färber2012-10-171-3/+8
* target-mips: Clean up other_cpu in helper_{d,e}vpe()Andreas Färber2012-10-171-14/+14
* Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson2012-09-271-1/+2
* target-mips: Implement Loongson Multimedia InstructionsRichard Henderson2012-09-194-4/+1180
* target-mips: Always evaluate debugging macro argumentsRichard Henderson2012-09-191-14/+17
* target-mips: Fix MIPS_DEBUG.Richard Henderson2012-09-191-36/+38
OpenPOWER on IntegriCloud