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* target-mips: Use cpu_exec_interrupt qom hookRichard Henderson2014-09-253-0/+19
| | | | | | | | | Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Tested-by: Leon Alrae <leon.alrae@imgtec.com> Message-id: 1410626734-3804-19-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova2014-08-121-0/+3
| | | | | Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* target-mips: Ignore unassigned accesses with KVMJames Hogan2014-08-071-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS registers an unassigned access handler which raises a guest bus error exception. However this causes QEMU to crash when KVM is enabled as it isn't called from the main execution loop so longjmp() gets called without a corresponding setjmp(). Until the KVM API can be updated to trigger a guest exception in response to an MMIO exit, prevent the bus error exception being raised from mips_cpu_unassigned_access() if KVM is enabled. The check is at run time since the do_unassigned_access callback is initialised before it is known whether KVM will be enabled. The problem can be triggered with Malta emulation by making the guest write to the reset region at physical address 0x1bf00000, since it is marked read-only which is treated as unassigned for writes. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@redhat.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-mips/translate.c: Free TCG in OPC_DINSVDongxue Zhang2014-07-281-0/+3
| | | | | | | Free t0 and t1 in opcode OPC_DINSV. Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* mips/kvm: Disable FPU on reset with KVMJames Hogan2014-07-091-0/+7
| | | | | | | | | | | | | | | | KVM doesn't yet support the MIPS FPU, or writing to the guest's Config1 register which contains the FPU implemented bit. Clear QEMU's version of that bit on reset and display a warning that the FPU has been disabled. The previous incorrect Config1 CP0 register value wasn't being passed to KVM yet, however we should ensure it is set correctly now to reduce the risk of breaking migration/loadvm to a future version of QEMU/Linux that does support it. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* mips/kvm: Init EBase to correct KSEG0James Hogan2014-07-051-1/+7
| | | | | | | | | | | | | | The EBase CP0 register is initialised to 0x80000000, however with KVM the guest's KSEG0 is at 0x40000000. The incorrect value doesn't get passed to KVM yet as KVM doesn't implement the EBase register, however we should set it correctly now so as not to break migration/loadvm to a future version of QEMU that does support EBase. Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-mips: copy CP0_Config1 into DisasContextAurelien Jarno2014-06-201-9/+11
| | | | | | | | In order to avoid access to the CPUMIPSState structure in the translator, keep a copy of CP0_Config1 into DisasContext. The whole register is read-only so it can be copied as a single value. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Merge remote-tracking branch 'remotes/kvm/uq/master' into stagingPeter Maydell2014-06-206-13/+758
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * remotes/kvm/uq/master: hw/mips: malta: Don't boot from flash with KVM T&E MAINTAINERS: Add entry for MIPS KVM target-mips: Enable KVM support in build system hw/mips: malta: Add KVM support hw/mips: In KVM mode, inject IRQ2 (I/O) interrupts via ioctls target-mips: Call kvm_mips_reset_vcpu() from mips_cpu_reset() target-mips: kvm: Add main KVM support for MIPS kvm: Allow arch to set sigmask length target-mips: get_physical_address: Add KVM awareness target-mips: get_physical_address: Add defines for segment bases hw/mips: Add API to convert KVM guest KSEG0 <-> GPA hw/mips/cputimer: Don't start periodic timer in KVM mode target-mips: Reset CPU timer consistently KVM: Fix GSI number space limit Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-mips: Enable KVM support in build systemSanjay Lal2014-06-181-0/+1
| | | | | | | | | | | | | | | | | | Enable KVM support for MIPS in the build system. Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-mips: Call kvm_mips_reset_vcpu() from mips_cpu_reset()James Hogan2014-06-181-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | When KVM is enabled call kvm_mips_reset_vcpu() from mips_cpu_reset() as done for other targets since commit 50a2c6e55fa2 (kvm: reset state from the CPU's reset method). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-mips: kvm: Add main KVM support for MIPSSanjay Lal2014-06-182-0/+709
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement the main KVM arch API for MIPS. Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Gleb Natapov <gleb@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Andreas Färber <afaerber@suse.de> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-mips: get_physical_address: Add KVM awarenessJames Hogan2014-06-181-7/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS KVM trap & emulate mode (which is currently the only supported mode) has to add an extra kseg0/kseg1 at 0x40000000 and an extra kseg2/kseg3 at 0x60000000. Take this into account in get_physical_address() so that debug memory access works. This is done by translating the address to a standard kseg0 or kseg2 address before doing the normal address translation. The real virtual address is still used for TLB lookups. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-mips: get_physical_address: Add defines for segment basesJames Hogan2014-06-181-6/+12
| | | | | | | | | | | | | | | | | | | | Add preprocessor definitions for 32bit segment bases for use in get_physical_address(). These will also be taken advantage of in the next patch which adds KVM awareness. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-mips: Reset CPU timer consistentlyJames Hogan2014-06-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS CPU timer (CP0 Count/Compare registers & QEMU timer) is reset at machine initialisation, including starting the timeout. Both registers however are placed before mvp in CPUMIPSState so they will both be zeroed on reset by the memset in mips_cpu_reset() including soon after init. This doesn't take into account that the timer may be running, in which case env->CP0_Count will represent the delta against the VM clock and the timeout will need updating. At init time (cpu_mips_clock_init()), lets only create the timer. Setting Count = 1 and starting the timer (cpu_mips_store_count()) can be done at reset time from cpu_state_reset(), which is after the memset. There is also no need to set CP0_Compare = 0 as that is already handled by the memset. Note that a reset occurs from mips_cpu_realizefn() which is before the machine init callback has had a chance to set up the CPU interrupts and the CPU timer, so env->timer will be NULL. This case is handled explicitly in cpu_mips_store_count(), treating the timer as disabled (which will also be the right thing to do when KVM support is added). Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | target-mips: implement UserLocal RegisterPetar Jovanovic2014-06-184-13/+83
|/ | | | | | | | | | | | | | | | | | | | | | From MIPS documentation (Volume III): UserLocal Register (CP0 Register 4, Select 2) Compliance Level: Recommended. The UserLocal register is a read-write register that is not interpreted by the hardware and conditionally readable via the RDHWR instruction. This register only exists if the Config3-ULRI register field is set. Privileged software may write this register with arbitrary information and make it accessible to unprivileged software via register 29 (ULR) of the RDHWR instruction. To do so, bit 29 of the HWREna register must be set to a 1 to enable unprivileged access to the register. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-052-5/+2
| | | | | | | | | | This will collect all load and store helpers soon. For now it is just a replacement for softmmu_exec.h, which this patch stops including directly, but we also include it where this will be necessary in order to simplify the next patch. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: commonize helper definitionsPaolo Bonzini2014-06-051-14/+0
| | | | | | | | | They do not need to be in op_helper.c. Because cputlb.c now includes softmmu_template.h twice for each size, io_readX must be elided the second time through. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini2014-06-052-1/+1
| | | | | | | Prepare for moving softmmu_header.h inclusion out of .c files Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: make do_unaligned_access a method of CPUPaolo Bonzini2014-06-053-6/+8
| | | | | | | | | We will reference it from more files in the next patch. To avoid ruining the small steps we're making towards multi-target, make it a method of CPU rather than just a global. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-285-12/+5
| | | | | | | | | | Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-mips: Avoid shifting left into sign bitPeter Maydell2014-03-274-17/+17
| | | | | | | | Add U suffix to various places where we shift a 1 left by 31, to avoid undefined behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 modePetar Jovanovic2014-03-251-35/+44
| | | | | | | | | | | Previous implementation presumed that FPU registers are 64-bit and are working in 64-bit mode. This change first checks MIPS_HFLAG_F64 and if not set, it does load/store from the odd numbered register pair. Patch by Matthew Fortune. Signed-off-by: Matthew Fortune <matthew.fortune@imgtec.com> Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* cputlb: Change tlb_set_page() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cputlb: Change tlb_flush() argument to CPUStateAndreas Färber2014-03-133-3/+6
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cputlb: Change tlb_flush_page() argument to CPUStateAndreas Färber2014-03-131-2/+6
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* exec: Change cpu_abort() argument to CPUStateAndreas Färber2014-03-132-3/+12
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* translate-all: Change cpu_restore_state() argument to CPUStateAndreas Färber2014-03-131-1/+1
| | | | | | This lets us drop some local variables in tlb_fill() functions. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu-exec: Change cpu_loop_exit() argument to CPUStateAndreas Färber2014-03-131-2/+2
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* exec: Change tlb_fill() argument to CPUStateAndreas Färber2014-03-131-3/+4
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move breakpoints field from CPU_COMMON to CPUStateAndreas Färber2014-03-133-3/+4
| | | | | | | | Most targets were using offsetof(CPUFooState, breakpoints) to determine how much of CPUFooState to clear on reset. Use the next field after CPU_COMMON instead, if any, or sizeof(CPUFooState) otherwise. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Move exception_index field from CPU_COMMON to CPUStateAndreas Färber2014-03-133-20/+24
| | | | Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Turn cpu_handle_mmu_fault() into a CPUClass hookAndreas Färber2014-03-134-11/+16
| | | | | | | | Note that while such functions may exist both for *-user and softmmu, only *-user uses the CPUState hook, while softmmu reuses the prototype for calling it directly. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Turn cpu_has_work() into a CPUClass hookAndreas Färber2014-03-132-28/+30
| | | | | | | | | Default to false. Tidy variable naming and inline cast uses while at it. Tested-by: Jia Liu <proljc@gmail.com> (or32) Signed-off-by: Andreas Färber <afaerber@suse.de>
* target-mips: add user-mode FR switch support for MIPS32r5Petar Jovanovic2014-02-104-10/+56
| | | | | | | | | | | | | | | | Description of UFR feature: Required in MIPS32r5 if floating point is implemented and user-mode FR switching is supported. The UFR register allows user-mode to clear StatusFR by executing a CTC1 to UFR with GPR[0] as input, and read StatusFR by executing a CFC1 to UFR. helper_ctc1 has been extended with an additional parameter rt to check requirements for UFR feature. Definition of mips32r5-generic has been modified to include support for UFR. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
* target-mips: add support for CP0_Config5Petar Jovanovic2014-02-105-3/+40
| | | | | | | Add CP0_Config5, define rw_bitmask and enable modifications. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
* target-mips: add support for CP0_Config4Petar Jovanovic2014-02-105-3/+31
| | | | | | | Add CP0_Config4, define rw_bitmask. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
* target-mips: add CPU definition for MIPS32R5Petar Jovanovic2014-02-102-0/+33
| | | | | | | | Add mips32r5-generic among CPU definitions for MIPS. Define ISA_MIPS32R3 and ISA_MIPS32R5. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Eric Johnson <eric.johnson@imgtec.com>
* target-mips: Use new qemu_ld/st opcodesAurelien Jarno2013-12-211-67/+52
| | | | | Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Use macro ARRAY_SIZE where possibleStefan Weil2013-12-091-18/+12
| | | | | | | | This improves readability and simplifies the code. Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Stefan Weil <sw@weilnetz.de> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix 64-bit FPU config for user-mode emulationPetar Jovanovic2013-12-091-2/+5
| | | | | | | | | | | FR bit should be initialized to 1 for MIPS64, under condition that this bit is writable and that CPU has an FPU unit. It should be initialized to zero for MIPS32. This fixes different MIPS32 issues with FPU instructions whose behaviour defaulted to 64-bit FPU mode. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* misc: Replace 'struct QEMUTimer' by 'QEMUTimer'Stefan Weil2013-12-021-1/+1
| | | | | | | | Most code already used QEMUTimer without the redundant 'struct' keyword. Signed-off-by: Stefan Weil <sw@weilnetz.de> Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* Merge remote-tracking branch 'rth/tcg-pull' into stagingAnthony Liguori2013-10-112-10/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | # By Richard Henderson # Via Richard Henderson * rth/tcg-pull: exec: Add both big- and little-endian memory helpers tcg: Add qemu_ld_st_i32/64 tcg: Add TCGMemOp configure: Remove CONFIG_QEMU_LDST_OPTIMIZATION tcg: Add tcg-be-ldst.h tcg: Add tcg-be-null.h exec: Delete is_tcg_gen_code and GETRA_EXT tcg-aarch64: Update to helper_ret_*_mmu routines tcg: Merge tcg_register_helper into tcg_context_init tcg: Add tcg-runtime.c helpers to all_helpers tcg: Put target helper data into an array. tcg: Remove stray semi-colons from target-*/helper.h tcg: Move helper registration into tcg_context_init target-m68k: Rename helpers.h to helper.h tcg: Use a GHashTable for tcg_find_helper tcg: Delete tcg_helper_get_name declaration tcg-hppa: Remove tcg backend Message-id: 1381440525-6666-1-git-send-email-rth@twiddle.net Signed-off-by: Anthony Liguori <aliguori@amazon.com>
| * tcg: Remove stray semi-colons from target-*/helper.hRichard Henderson2013-10-101-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During GEN_HELPER=1, these are actually stray top-level semi-colons which are technically invalid ISO C, but GCC accepts as an extension. If we added enough __extension__ markers that we could dare use -Wpedantic, we'd see warning: ISO C does not allow extra ‘;’ outside of a function This will become a hard error in the next patch, wherein those ; will appear in the middle of a data structure. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
| * tcg: Move helper registration into tcg_context_initRichard Henderson2013-10-101-4/+0
| | | | | | | | | | | | No longer needs to be done on a per-target basis. Signed-off-by: Richard Henderson <rth@twiddle.net>
* | cpu: Drop cpu_model_str from CPU_COMMONAndreas Färber2013-10-071-1/+0
|/ | | | | | | Since this is only read in cpu_copy() and linux-user has a global cpu_model, drop the field from generic code. Signed-off-by: Andreas Färber <afaerber@suse.de>
* cpu: Use QTAILQ for CPU listAndreas Färber2013-09-031-6/+4
| | | | | | | Introduce CPU_FOREACH(), CPU_FOREACH_SAFE() and CPU_NEXT() shorthand macros. Signed-off-by: Andreas Färber <afaerber@suse.de>
* tcg: Change tcg_gen_exit_tb argument to uintptr_tRichard Henderson2013-09-021-1/+1
| | | | | | | And update all users. Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-mips: fix get_physical_address() #if 0 build errorJames Hogan2013-08-281-1/+1
| | | | | | | | | | | | | | | | In get_physical_address() is a qemu_log() call inside an #if 0 block. When enabled the following build error is hit: target-mips/helper.c In function ‘get_physical_address’: target-mips/helper.c:220:13: error: format ‘%x’ expects argument of type ‘unsigned int’, but argument 5 has type ‘hwaddr’ [-Werror=format] Fix the *physical (hwaddr) formatting by using "%"HWADDR_PRIx instead of TARGET_FMT_lx. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix decoding of microMIPS POOL32Axf instructionsLeon Alrae2013-08-061-6/+54
| | | | | | | | | | | | | | | | Fix incorrect assumption that DSP and non-DSP versions of the following instructions have the same encoding: MULT, MULTU, MADD, MADDU, MSUB, MSUBU, MFHI, MFLO, MTHI, MTLO. Correct the existing (non-DSP) instructions and add DSP equivalents. Reference: MIPS Architecture for Programmers Volume II-B: The microMIPS32 Instruction Set MIPS Architecture for Programmers Volume IV-e: The MIPS DSP Module for the microMIPS32 Architecture Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: fix 34Kf configuration for DSP ASEYongbok Kim2013-08-031-4/+3
| | | | | | | | | | 34Kf core does support DSP ASE. CP0_Config3 configuration for 34Kf and description are wrong. Please refer to MIPS32(R) 34Kf(TM) Processor Core Datasheet Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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