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* target-mips: add ULL suffix in bitswap to avoid compiler warningLeon Alrae2014-10-241-6/+6
| | | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Message-id: 1413982829-27225-1-git-send-email-leon.alrae@imgtec.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACXPeter Maydell2014-10-141-19/+1
| | | | | | | | | | | Remove the functions gen_load_ACX and gen_store_ACX, which appear to have been unused since they were first introduced many years ago. These functions were the only places using the cpu_ACX[] array of TCG globals, so remove that and its accompanying regnames_ACX[] as well. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips/dsp_helper.c: Add ifdef guards around various functionsPeter Maydell2014-10-141-1/+16
| | | | | | | | | | Add ifdef TARGET_MIPS64 guards around various functions that are only called from helpers for TARGET_MIPS64 CPUs; this avoids compiler warnings when building other configs. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips/translate.c: Add ifdef guard around check_mips64()Peter Maydell2014-10-141-0/+2
| | | | | | | | | | The function check_mips64() is only used if TARGET_MIPS64 is defined; add an ifdef guard to its definition to avoid warnings about it being unused in other configurations. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips/op_helper.c: Remove unused do_lbu() functionPeter Maydell2014-10-141-1/+0
| | | | | | | | | The do_lbu() function defined by the expansion of HELPER_LD() is never used, so don't define it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips/dsp_helper.c: Remove unused function get_DSPControl_24()Peter Maydell2014-10-141-9/+0
| | | | | | | | The function get_DSPControl_24() is unused; remove it. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: fix broken MIPS16 and microMIPSYongbok Kim2014-10-142-188/+123
| | | | | | | | | | | | | | | | | | | | | | | | Commit 240ce26a broke MIPS16 and microMIPS support as it didn't care those branches and jumps don't have delay slot in MIPS16 and microMIPS. This patch introduces a new argument delayslot_size to the gen_compute_branch() indicating size of delay slot {0, 2, 4}. And the information is used to call handle_delay_slot() forcingly when no delay slot is required. There are some microMIPS branch and jump instructions that requires exact size of instruction in the delay slot. For indicating these instructions, MIPS_HFLAG_BDS_STRICT flag is introduced. Those fictional branch opcodes defined to support MIPS16 and microMIPS are no longer needed. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Tested-by: Jonas Gorski <jogo@openwrt.org> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> [leon.alrae@imgtec.com: cosmetic changes] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips/translate.c: Update OPC_SYNCIDongxue Zhang2014-10-141-1/+6
| | | | | | | | | | Update OPC_SYNCI with BS_STOP, in order to handle the instructions which saved in the same TB of the store instruction. Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com> [leon.alrae@imgtec.com: update microMIPS SYNCI as well] Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: define a new generic CPU supporting MIPS64 Release 6 ISALeon Alrae2014-10-141-0/+30
| | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
* target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructionsYongbok Kim2014-10-141-2/+16
| | | | | | Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: do not allow Status.FR=0 mode in 64-bit FPULeon Alrae2014-10-141-0/+6
| | | | | | | | | Status.FR bit must be ignored on write and read as 1 when an implementation of Release 6 of the Architecture in which a 64-bit floating point unit is implemented. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
* target-mips: add new Floating Point Comparison instructionsYongbok Kim2014-10-143-2/+342
| | | | | | Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: add new Floating Point instructionsLeon Alrae2014-10-143-44/+521
| | | | | | | | | | | | In terms of encoding MIPS32R6 MIN.fmt, MAX.fmt, MINA.fmt, MAXA.fmt replaced MIPS-3D RECIP1, RECIP2, RSQRT1, RSQRT2 instructions. In R6 all Floating Point instructions are supposed to be IEEE-2008 compliant i.e. FIR.HAS2008 always 1. However, QEMU softfloat for MIPS has not been updated yet. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
* target-mips: add AUI, LSA and PCREL instruction familiesLeon Alrae2014-10-141-14/+189
| | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
* target-mips: add compact and CP1 branchesYongbok Kim2014-10-131-14/+459
| | | | | | | | | | | Introduce MIPS32R6 Compact Branch instructions which do not have delay slot - they have forbidden slot instead. However, current implementation does not support forbidden slot yet. Add also BC1EQZ and BC1NEZ instructions. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
* target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructionsYongbok Kim2014-10-133-12/+136
| | | | | | Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: Status.UX/SX/KX enable 32-bit address wrappingLeon Alrae2014-10-132-9/+15
| | | | | | | | | In R6 the special behaviour for data references is also specified for Kernel and Supervisor mode. Therefore MIPS_HFLAG_UX is replaced by generic MIPS_HFLAG_AWRAP indicating enabled 32-bit address wrapping. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6Leon Alrae2014-10-131-59/+62
| | | | | | | | Also consider OPC_SPIM instruction as deleted in R6 because it is overlaping with MIPS32R6 SDBBP. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: redefine Integer Multiply and Divide instructionsLeon Alrae2014-10-131-21/+322
| | | | | | | | Use "R6_" prefix in front of all new Multiply / Divide instructions for easier differentiation between R6 and preR6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: move PREF, CACHE, LLD and SCD instructionsLeon Alrae2014-10-131-1/+28
| | | | | | | | | The encoding of PREF, CACHE, LLD and SCD instruction changed in MIPS32R6. Additionally, the hint codes in PREF instruction greater than or equal to 24 generate Reserved Instruction Exception. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: signal RI Exception on DSP and Loongson instructionsLeon Alrae2014-10-131-97/+98
| | | | | | | | Move DSP and Loongson instruction to *_legacy functions as they have been removed in R6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: split decode_opc_special* into *_r6 and *_legacyLeon Alrae2014-10-131-68/+160
| | | | | | | | | | | | For better code readability and to avoid 'if' statements for all R6 and preR6 instructions whose opcodes are the same - decode_opc_special* functions are split into functions with _r6 and _legacy suffixes. *_r6 functions will contain instructions which were introduced in R6. *_legacy functions will contain instructions which were removed in R6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: extract decode_opc_special* from decode_opcLeon Alrae2014-10-131-805/+845
| | | | | | | | | Creating separate decode functions for special, special2 and special3 instructions to ease adding new R6 instructions and removing legacy instructions. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: move LL and SC instructionsLeon Alrae2014-10-131-2/+26
| | | | | | | | The encoding of LL and SC instruction has changed in MIPS32 Release 6. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: James Hogan <james.hogan@imgtec.com>
* target-mips: add SELEQZ and SELNEZ instructionsLeon Alrae2014-10-131-2/+16
| | | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: James Hogan <james.hogan@imgtec.com>
* target-mips: signal RI Exception on instructions removed in R6Leon Alrae2014-10-131-8/+56
| | | | | | | | | | | | | | | | | Signal Reserved Instruction Exception on instructions that do not exist in R6. In this commit the following groups of preR6 instructions are marked as deleted: - Floating Point Paired Single - Floating Point Compare - conditional moves / branches on FPU conditions - branch likelies - unaligned loads / stores - traps - legacy accumulator instructions - COP1X - MIPS-3D Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* target-mips: define ISA_MIPS64R6Leon Alrae2014-10-131-9/+19
| | | | | Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
* gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flagPeter Maydell2014-10-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | GDB assumes that watchpoint set via the gdbstub remote protocol will behave in the same way as hardware watchpoints for the target. In particular, whether the CPU stops with the PC before or after the insn which triggers the watchpoint is target dependent. Allow guest CPU code to specify which behaviour to use. This fixes a bug where with guest CPUs which stop before the accessing insn GDB would manually step forward over what it thought was the insn and end up one insn further forward than it should be. We set this flag for the CPU architectures which set gdbarch_have_nonsteppable_watchpoint in gdb 7.7: ARM, CRIS, LM32, MIPS and Xtensa. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Max Filippov <jcmvbkbc@gmail.com> Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Tested-by: Michael Walle <michael@walle.cc> (for lm32) Message-id: 1410545057-14014-1-git-send-email-peter.maydell@linaro.org
* target-mips: Use cpu_exec_interrupt qom hookRichard Henderson2014-09-253-0/+19
| | | | | | | | | Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Richard Henderson <rth@twiddle.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Tested-by: Leon Alrae <leon.alrae@imgtec.com> Message-id: 1410626734-3804-19-git-send-email-rth@twiddle.net Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova2014-08-121-0/+3
| | | | | Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu> Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
* target-mips: Ignore unassigned accesses with KVMJames Hogan2014-08-071-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS registers an unassigned access handler which raises a guest bus error exception. However this causes QEMU to crash when KVM is enabled as it isn't called from the main execution loop so longjmp() gets called without a corresponding setjmp(). Until the KVM API can be updated to trigger a guest exception in response to an MMIO exit, prevent the bus error exception being raised from mips_cpu_unassigned_access() if KVM is enabled. The check is at run time since the do_unassigned_access callback is initialised before it is known whether KVM will be enabled. The problem can be triggered with Malta emulation by making the guest write to the reset region at physical address 0x1bf00000, since it is marked read-only which is treated as unassigned for writes. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Cc: Peter Maydell <peter.maydell@linaro.org> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@redhat.com> Cc: Christoffer Dall <christoffer.dall@linaro.org> Cc: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-mips/translate.c: Free TCG in OPC_DINSVDongxue Zhang2014-07-281-0/+3
| | | | | | | Free t0 and t1 in opcode OPC_DINSV. Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* mips/kvm: Disable FPU on reset with KVMJames Hogan2014-07-091-0/+7
| | | | | | | | | | | | | | | | KVM doesn't yet support the MIPS FPU, or writing to the guest's Config1 register which contains the FPU implemented bit. Clear QEMU's version of that bit on reset and display a warning that the FPU has been disabled. The previous incorrect Config1 CP0 register value wasn't being passed to KVM yet, however we should ensure it is set correctly now to reduce the risk of breaking migration/loadvm to a future version of QEMU/Linux that does support it. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* mips/kvm: Init EBase to correct KSEG0James Hogan2014-07-051-1/+7
| | | | | | | | | | | | | | The EBase CP0 register is initialised to 0x80000000, however with KVM the guest's KSEG0 is at 0x40000000. The incorrect value doesn't get passed to KVM yet as KVM doesn't implement the EBase register, however we should set it correctly now so as not to break migration/loadvm to a future version of QEMU that does support EBase. Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* target-mips: copy CP0_Config1 into DisasContextAurelien Jarno2014-06-201-9/+11
| | | | | | | | In order to avoid access to the CPUMIPSState structure in the translator, keep a copy of CP0_Config1 into DisasContext. The whole register is read-only so it can be copied as a single value. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* Merge remote-tracking branch 'remotes/kvm/uq/master' into stagingPeter Maydell2014-06-206-13/+758
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * remotes/kvm/uq/master: hw/mips: malta: Don't boot from flash with KVM T&E MAINTAINERS: Add entry for MIPS KVM target-mips: Enable KVM support in build system hw/mips: malta: Add KVM support hw/mips: In KVM mode, inject IRQ2 (I/O) interrupts via ioctls target-mips: Call kvm_mips_reset_vcpu() from mips_cpu_reset() target-mips: kvm: Add main KVM support for MIPS kvm: Allow arch to set sigmask length target-mips: get_physical_address: Add KVM awareness target-mips: get_physical_address: Add defines for segment bases hw/mips: Add API to convert KVM guest KSEG0 <-> GPA hw/mips/cputimer: Don't start periodic timer in KVM mode target-mips: Reset CPU timer consistently KVM: Fix GSI number space limit Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| * target-mips: Enable KVM support in build systemSanjay Lal2014-06-181-0/+1
| | | | | | | | | | | | | | | | | | Enable KVM support for MIPS in the build system. Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-mips: Call kvm_mips_reset_vcpu() from mips_cpu_reset()James Hogan2014-06-181-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | When KVM is enabled call kvm_mips_reset_vcpu() from mips_cpu_reset() as done for other targets since commit 50a2c6e55fa2 (kvm: reset state from the CPU's reset method). Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Gleb Natapov <gleb@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-mips: kvm: Add main KVM support for MIPSSanjay Lal2014-06-182-0/+709
| | | | | | | | | | | | | | | | | | | | | | | | | | Implement the main KVM arch API for MIPS. Signed-off-by: Sanjay Lal <sanjayl@kymasys.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Gleb Natapov <gleb@redhat.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: Andreas Färber <afaerber@suse.de> Cc: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-mips: get_physical_address: Add KVM awarenessJames Hogan2014-06-181-7/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MIPS KVM trap & emulate mode (which is currently the only supported mode) has to add an extra kseg0/kseg1 at 0x40000000 and an extra kseg2/kseg3 at 0x60000000. Take this into account in get_physical_address() so that debug memory access works. This is done by translating the address to a standard kseg0 or kseg2 address before doing the normal address translation. The real virtual address is still used for TLB lookups. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-mips: get_physical_address: Add defines for segment basesJames Hogan2014-06-181-6/+12
| | | | | | | | | | | | | | | | | | | | Add preprocessor definitions for 32bit segment bases for use in get_physical_address(). These will also be taken advantage of in the next patch which adds KVM awareness. Signed-off-by: James Hogan <james.hogan@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| * target-mips: Reset CPU timer consistentlyJames Hogan2014-06-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MIPS CPU timer (CP0 Count/Compare registers & QEMU timer) is reset at machine initialisation, including starting the timeout. Both registers however are placed before mvp in CPUMIPSState so they will both be zeroed on reset by the memset in mips_cpu_reset() including soon after init. This doesn't take into account that the timer may be running, in which case env->CP0_Count will represent the delta against the VM clock and the timeout will need updating. At init time (cpu_mips_clock_init()), lets only create the timer. Setting Count = 1 and starting the timer (cpu_mips_store_count()) can be done at reset time from cpu_state_reset(), which is after the memset. There is also no need to set CP0_Compare = 0 as that is already handled by the memset. Note that a reset occurs from mips_cpu_realizefn() which is before the machine init callback has had a chance to set up the CPU interrupts and the CPU timer, so env->timer will be NULL. This case is handled explicitly in cpu_mips_store_count(), treating the timer as disabled (which will also be the right thing to do when KVM support is added). Reported-by: Paolo Bonzini <pbonzini@redhat.com> Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* | target-mips: implement UserLocal RegisterPetar Jovanovic2014-06-184-13/+83
|/ | | | | | | | | | | | | | | | | | | | | | From MIPS documentation (Volume III): UserLocal Register (CP0 Register 4, Select 2) Compliance Level: Recommended. The UserLocal register is a read-write register that is not interpreted by the hardware and conditionally readable via the RDHWR instruction. This register only exists if the Config3-ULRI register field is set. Privileged software may write this register with arbitrary information and make it accessible to unprivileged software via register 29 (ULR) of the RDHWR instruction. To do so, bit 29 of the HWREna register must be set to a 1 to enable unprivileged access to the register. Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-052-5/+2
| | | | | | | | | | This will collect all load and store helpers soon. For now it is just a replacement for softmmu_exec.h, which this patch stops including directly, but we also include it where this will be necessary in order to simplify the next patch. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: commonize helper definitionsPaolo Bonzini2014-06-051-14/+0
| | | | | | | | | They do not need to be in op_helper.c. Because cputlb.c now includes softmmu_template.h twice for each size, io_readX must be elided the second time through. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini2014-06-052-1/+1
| | | | | | | Prepare for moving softmmu_header.h inclusion out of .c files Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* softmmu: make do_unaligned_access a method of CPUPaolo Bonzini2014-06-053-6/+8
| | | | | | | | | We will reference it from more files in the next patch. To avoid ruining the small steps we're making towards multi-target, make it a method of CPU rather than just a global. Reviewed-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-285-12/+5
| | | | | | | | | | Rather than include helper.h with N values of GEN_HELPER, include a secondary file that sets up the macros to include helper.h. This minimizes the files that must be rebuilt when changing the macros for file N. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
* target-mips: Avoid shifting left into sign bitPeter Maydell2014-03-274-17/+17
| | | | | | | | Add U suffix to various places where we shift a 1 left by 31, to avoid undefined behaviour. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
* target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 modePetar Jovanovic2014-03-251-35/+44
| | | | | | | | | | | Previous implementation presumed that FPU registers are 64-bit and are working in 64-bit mode. This change first checks MIPS_HFLAG_F64 and if not set, it does load/store from the odd numbered register pair. Patch by Matthew Fortune. Signed-off-by: Matthew Fortune <matthew.fortune@imgtec.com> Signed-off-by: Petar Jovanovic <petar.jovanovic@imgtec.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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