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* target-mips: add ULL suffix in bitswap to avoid compiler warningLeon Alrae2014-10-241-6/+6
* target-mips: Remove unused gen_load_ACX, gen_store_ACX and cpu_ACXPeter Maydell2014-10-141-19/+1
* target-mips/dsp_helper.c: Add ifdef guards around various functionsPeter Maydell2014-10-141-1/+16
* target-mips/translate.c: Add ifdef guard around check_mips64()Peter Maydell2014-10-141-0/+2
* target-mips/op_helper.c: Remove unused do_lbu() functionPeter Maydell2014-10-141-1/+0
* target-mips/dsp_helper.c: Remove unused function get_DSPControl_24()Peter Maydell2014-10-141-9/+0
* target-mips: fix broken MIPS16 and microMIPSYongbok Kim2014-10-142-188/+123
* target-mips/translate.c: Update OPC_SYNCIDongxue Zhang2014-10-141-1/+6
* target-mips: define a new generic CPU supporting MIPS64 Release 6 ISALeon Alrae2014-10-141-0/+30
* target-mips: remove JR, BLTZAL, BGEZAL and add NAL, BAL instructionsYongbok Kim2014-10-141-2/+16
* target-mips: do not allow Status.FR=0 mode in 64-bit FPULeon Alrae2014-10-141-0/+6
* target-mips: add new Floating Point Comparison instructionsYongbok Kim2014-10-143-2/+342
* target-mips: add new Floating Point instructionsLeon Alrae2014-10-143-44/+521
* target-mips: add AUI, LSA and PCREL instruction familiesLeon Alrae2014-10-141-14/+189
* target-mips: add compact and CP1 branchesYongbok Kim2014-10-131-14/+459
* target-mips: add ALIGN, DALIGN, BITSWAP and DBITSWAP instructionsYongbok Kim2014-10-133-12/+136
* target-mips: Status.UX/SX/KX enable 32-bit address wrappingLeon Alrae2014-10-132-9/+15
* target-mips: move CLO, DCLO, CLZ, DCLZ, SDBBP and free special2 in R6Leon Alrae2014-10-131-59/+62
* target-mips: redefine Integer Multiply and Divide instructionsLeon Alrae2014-10-131-21/+322
* target-mips: move PREF, CACHE, LLD and SCD instructionsLeon Alrae2014-10-131-1/+28
* target-mips: signal RI Exception on DSP and Loongson instructionsLeon Alrae2014-10-131-97/+98
* target-mips: split decode_opc_special* into *_r6 and *_legacyLeon Alrae2014-10-131-68/+160
* target-mips: extract decode_opc_special* from decode_opcLeon Alrae2014-10-131-805/+845
* target-mips: move LL and SC instructionsLeon Alrae2014-10-131-2/+26
* target-mips: add SELEQZ and SELNEZ instructionsLeon Alrae2014-10-131-2/+16
* target-mips: signal RI Exception on instructions removed in R6Leon Alrae2014-10-131-8/+56
* target-mips: define ISA_MIPS64R6Leon Alrae2014-10-131-9/+19
* gdbstub: Allow target CPUs to specify watchpoint STOP_BEFORE_ACCESS flagPeter Maydell2014-10-061-0/+1
* target-mips: Use cpu_exec_interrupt qom hookRichard Henderson2014-09-253-0/+19
* trace: [tcg] Include TCG-tracing header on all targetsLluís Vilanova2014-08-121-0/+3
* target-mips: Ignore unassigned accesses with KVMJames Hogan2014-08-071-0/+11
* target-mips/translate.c: Free TCG in OPC_DINSVDongxue Zhang2014-07-281-0/+3
* mips/kvm: Disable FPU on reset with KVMJames Hogan2014-07-091-0/+7
* mips/kvm: Init EBase to correct KSEG0James Hogan2014-07-051-1/+7
* target-mips: copy CP0_Config1 into DisasContextAurelien Jarno2014-06-201-9/+11
* Merge remote-tracking branch 'remotes/kvm/uq/master' into stagingPeter Maydell2014-06-206-13/+758
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| * target-mips: Enable KVM support in build systemSanjay Lal2014-06-181-0/+1
| * target-mips: Call kvm_mips_reset_vcpu() from mips_cpu_reset()James Hogan2014-06-181-0/+8
| * target-mips: kvm: Add main KVM support for MIPSSanjay Lal2014-06-182-0/+709
| * target-mips: get_physical_address: Add KVM awarenessJames Hogan2014-06-181-7/+26
| * target-mips: get_physical_address: Add defines for segment basesJames Hogan2014-06-181-6/+12
| * target-mips: Reset CPU timer consistentlyJames Hogan2014-06-181-0/+2
* | target-mips: implement UserLocal RegisterPetar Jovanovic2014-06-184-13/+83
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* softmmu: introduce cpu_ldst.hPaolo Bonzini2014-06-052-5/+2
* softmmu: commonize helper definitionsPaolo Bonzini2014-06-051-14/+0
* softmmu: move ALIGNED_ONLY to cpu.hPaolo Bonzini2014-06-052-1/+1
* softmmu: make do_unaligned_access a method of CPUPaolo Bonzini2014-06-053-6/+8
* tcg: Invert the inclusion of helper.hRichard Henderson2014-05-285-12/+5
* target-mips: Avoid shifting left into sign bitPeter Maydell2014-03-274-17/+17
* target-mips: fix MTHC1 and MFHC1 when FPU in FR=0 modePetar Jovanovic2014-03-251-35/+44
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