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* fpu: move public header file to include/fpuPaolo Bonzini2012-12-191-1/+1
* misc: move include files to include/qemu/Paolo Bonzini2012-12-191-1/+1
* qom: move include files to include/qom/Paolo Bonzini2012-12-191-1/+1
* exec: move include files to include/exec/Paolo Bonzini2012-12-194-11/+11
* build: kill libdis, move disassemblers to disas/Paolo Bonzini2012-12-191-1/+1
* exec: refactor cpu_restore_stateBlue Swirl2012-12-161-7/+1
* Merge branch 'master' of git.qemu-project.org:/pub/git/qemuBlue Swirl2012-12-081-9/+10
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| * target-mips: Fix incorrect shift for SHILO and SHILOVPetar Jovanovic2012-12-061-8/+9
| * target-mips: Fix incorrect code and test for INSVPetar Jovanovic2012-12-061-1/+1
* | TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin2012-12-081-3/+3
* | TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin2012-12-081-1/+1
* | TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin2012-12-081-2/+2
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* target-mips: remove POOL48A from the microMIPS decodingAurelien Jarno2012-11-241-1/+0
* target-mips: Clean up microMIPS32 major opcode陳韋任 (Wei-Ren Chen)2012-11-241-7/+17
* target-mips: Add comments on POOL32Axf encoding陳韋任 (Wei-Ren Chen)2012-11-241-0/+17
* TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin2012-11-171-3/+3
* TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin2012-11-171-4/+5
* target-mips: fix wrong microMIPS opcode encoding陳韋任 (Wei-Ren Chen)2012-11-151-1/+1
* target-mips: Fix seg fault for LUI when MIPS_DEBUG_DISAS==1.Eric Johnson2012-11-111-7/+11
* disas: avoid using cpu_single_envBlue Swirl2012-11-101-1/+1
* target-mips: use ULL for 64 bit constantsBlue Swirl2012-11-051-2/+2
* Merge remote-tracking branch 'afaerber/qom-cpu' into stagingAnthony Liguori2012-11-011-5/+6
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| * cpus: Pass CPUState to [qemu_]cpu_has_work()Andreas Färber2012-10-311-5/+6
* | target-mips: don't flush extra TLB on permissions upgradeAurelien Jarno2012-10-311-5/+23
* | target-mips: fix TLBR wrt SEGMaskAurelien Jarno2012-10-311-0/+6
* | target-mips: use deposit instead of hardcoded versionAurelien Jarno2012-10-311-28/+4
* | target-mips: optimize ddiv/ddivu/div/divu with movcondAurelien Jarno2012-10-311-48/+37
* | target-mips: implement movn/movz using movcondAurelien Jarno2012-10-311-15/+12
* | target-mips: don't use local temps for store conditionalAurelien Jarno2012-10-311-5/+6
* | target-mips: implement unaligned loads using TCGAurelien Jarno2012-10-313-159/+62
* | target-mips: simplify load/store microMIPS helpersAurelien Jarno2012-10-311-64/+9
* | target-mips: optimize load operationsAurelien Jarno2012-10-311-4/+12
* | target-mips: cleanup load/store operationsAurelien Jarno2012-10-311-64/+35
* | target-mips: restore CPU state after an FPU exceptionAurelien Jarno2012-10-311-90/+95
* | target-mips: use softfloat constants when possibleAurelien Jarno2012-10-311-48/+44
* | target-mips: cleanup float to int conversion helpersAurelien Jarno2012-10-311-39/+79
* | target-mips: fix FPU exceptionsAurelien Jarno2012-10-311-13/+19
* | target-mips: keep softfloat exception set to 0 between instructionsAurelien Jarno2012-10-311-63/+10
* | target-mips: use the softfloat floatXX_muladd functionsAurelien Jarno2012-10-313-105/+64
* | target-mips: do not save CPU state when using retranslationAurelien Jarno2012-10-311-20/+0
* | target-mips: correctly restore btarget upon exceptionAurelien Jarno2012-10-311-0/+11
* | target-mips: remove #if defined(TARGET_MIPS64) in opcode enumsAurelien Jarno2012-10-311-36/+0
* | target-mips: Change TODO fileJia Liu2012-10-311-2/+1
* | target-mips: Add ASE DSP processorsJia Liu2012-10-311-0/+52
* | target-mips: Add ASE DSP accumulator instructionsJia Liu2012-10-313-0/+995
* | target-mips: Add ASE DSP compare-pick instructionsJia Liu2012-10-313-0/+635
* | target-mips: Add ASE DSP bit/manipulation instructionsJia Liu2012-10-313-0/+311
* | target-mips: Add ASE DSP multiply instructionsJia Liu2012-10-313-0/+1499
* | target-mips: Add ASE DSP GPR-based shift instructionsJia Liu2012-10-313-0/+618
* | target-mips: Add ASE DSP arithmetic instructionsJia Liu2012-10-313-3/+1812
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