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path: root/target-mips/translate_init.c
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* target-xxx: Use fprintf_function (format checking)Stefan Weil2010-10-301-1/+1
* Remove unused constantHervé Poussineau2010-07-311-4/+0
* MIPS: Initial support of fulong mini pc (CPU definition)Huacai Chen2010-06-291-0/+35
* target-mips: No MIPS16 support for 4Kc, 4KEc coresStefan Weil2009-12-171-3/+3
* target-mips: 4Kc, 4KEc cores do not support MIPS16Stefan Weil2009-12-161-3/+3
* target-mips: fix user-mode emulation startupNathan Froyd2009-12-131-8/+0
* target-mips: set Config1.CA for MIPS16-aware CPUsNathan Froyd2009-12-131-9/+18
* target-mips: make CP0_LLAddr register CPU dependentAurelien Jarno2009-11-221-0/+32
* mips: fix cpu_reset memory leakBlue Swirl2009-11-141-50/+0
* Revert "Get rid of _t suffix"Anthony Liguori2009-10-011-10/+10
* Get rid of _t suffixmalc2009-10-011-10/+10
* Update to a hopefully more future proof FSF addressBlue Swirl2009-07-161-2/+1
* target-mips: rename helpers from do_ to helper_aurel322009-03-081-4/+4
* target-mips: fix indentationaurel322009-01-141-42/+42
* target-mips: get rid of tests on env->user_mode_onlyaurel322009-01-121-10/+10
* Update FSF address in GPL/LGPL boilerplateaurel322009-01-041-1/+1
* Use the ARRAY_SIZE() macro where appropriate.malc2008-12-221-2/+2
* Move the active FPU registers into env again, and use more TCG registersths2008-09-181-3/+6
* target-mips: fix warningaurel322008-09-141-1/+1
* Build fix for gcc-3.3.ths2008-09-021-0/+4
* Less hardcoding of TARGET_USER_ONLY.ths2008-07-231-15/+12
* A bunch of minor code improvements in the MIPS target.ths2008-07-211-1/+1
* Fix compiler warning, by Stefan Weil.ths2008-07-201-1/+1
* More efficient target register / TC accesses.ths2008-06-271-2/+0
* Honour current_tc for MIPS M{T,F}{HI,LO}, by Richard Sandiford.ths2008-05-281-0/+1
* Enable 64-bit FPU only for NewABI. Spotted by Vince Weaver.ths2008-05-061-0/+2
* Use TCG for MIPS GPR moves.ths2008-05-061-0/+2
* Set FCR0.F64 for MIPS64R2-generic, by Richard Sandiford.ths2007-12-281-3/+3
* Support for VR5432, and some of its special instructions. Original patchths2007-12-251-0/+16
* 5K and 20K are Release 1 CPUs.ths2007-12-251-3/+3
* Improved PABITS handling, and config register fixes.ths2007-12-251-50/+99
* Fix CCRes value for 20Kc.ths2007-12-241-1/+1
* Add older 4Km variants.ths2007-11-191-0/+34
* Use a valid PRid.ths2007-11-181-1/+1
* Introduce 4KEm configuration with fixed MMU mapping. Delete bogus INSN_DSPths2007-11-141-2/+19
* added cpu_model parameter to cpu_init()bellard2007-11-101-22/+11
* Clean out the N32 macros from target-mips, and introduce MIPS ABI specificths2007-11-081-2/+2
* Preliminary MIPS64R2 mode.ths2007-10-291-0/+21
* Use the standard ASE check for MIPS-3D and MT.ths2007-10-231-1/+1
* Code provision for n32/n64 mips userland emulation. Not functional yet.ths2007-09-301-2/+2
* Supervisor mode implementation, by Aurelien Jarno.ths2007-09-291-3/+3
* Per-CPU instruction decoding implementation, by Aurelien Jarno.ths2007-09-241-1/+13
* Fix mips usermode emulation.ths2007-09-231-0/+3
* Partial support for 34K multithreading, not functional yet.ths2007-09-061-53/+158
* Disable 64-bit instructions on 32-bit CPU, by Aurelien Jarno.ths2007-08-261-7/+9
* Fix MIPS cache configuration, by Aurelien Jarno.ths2007-07-291-11/+19
* Handle MIPS64 SEGBITS value correctly.ths2007-06-231-0/+14
* Allow emulation of 32bit targets in the MIPS64 capable qemu version.ths2007-06-221-2/+1
* Change 20Kc PRID to a later version.ths2007-06-121-1/+3
* R5k has PX implemented.ths2007-06-091-2/+2
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