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path: root/target-mips/translate.c
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* exec: move include files to include/exec/Paolo Bonzini2012-12-191-1/+1
* build: kill libdis, move disassemblers to disas/Paolo Bonzini2012-12-191-1/+1
* TCG: Use gen_opc_instr_start from context instead of global variable.Evgeny Voevodin2012-12-081-3/+3
* TCG: Use gen_opc_icount from context instead of global variable.Evgeny Voevodin2012-12-081-1/+1
* TCG: Use gen_opc_pc from context instead of global variable.Evgeny Voevodin2012-12-081-2/+2
* target-mips: remove POOL48A from the microMIPS decodingAurelien Jarno2012-11-241-1/+0
* target-mips: Clean up microMIPS32 major opcode陳韋任 (Wei-Ren Chen)2012-11-241-7/+17
* target-mips: Add comments on POOL32Axf encoding陳韋任 (Wei-Ren Chen)2012-11-241-0/+17
* TCG: Use gen_opc_buf from context instead of global variable.Evgeny Voevodin2012-11-171-3/+3
* TCG: Use gen_opc_ptr from context instead of global variable.Evgeny Voevodin2012-11-171-4/+5
* target-mips: fix wrong microMIPS opcode encoding陳韋任 (Wei-Ren Chen)2012-11-151-1/+1
* target-mips: Fix seg fault for LUI when MIPS_DEBUG_DISAS==1.Eric Johnson2012-11-111-7/+11
* disas: avoid using cpu_single_envBlue Swirl2012-11-101-1/+1
* target-mips: use deposit instead of hardcoded versionAurelien Jarno2012-10-311-28/+4
* target-mips: optimize ddiv/ddivu/div/divu with movcondAurelien Jarno2012-10-311-48/+37
* target-mips: implement movn/movz using movcondAurelien Jarno2012-10-311-15/+12
* target-mips: don't use local temps for store conditionalAurelien Jarno2012-10-311-5/+6
* target-mips: implement unaligned loads using TCGAurelien Jarno2012-10-311-13/+62
* target-mips: optimize load operationsAurelien Jarno2012-10-311-4/+12
* target-mips: cleanup load/store operationsAurelien Jarno2012-10-311-64/+35
* target-mips: use the softfloat floatXX_muladd functionsAurelien Jarno2012-10-311-12/+12
* target-mips: do not save CPU state when using retranslationAurelien Jarno2012-10-311-20/+0
* target-mips: correctly restore btarget upon exceptionAurelien Jarno2012-10-311-0/+11
* target-mips: remove #if defined(TARGET_MIPS64) in opcode enumsAurelien Jarno2012-10-311-36/+0
* target-mips: Add ASE DSP accumulator instructionsJia Liu2012-10-311-0/+351
* target-mips: Add ASE DSP compare-pick instructionsJia Liu2012-10-311-0/+350
* target-mips: Add ASE DSP bit/manipulation instructionsJia Liu2012-10-311-0/+249
* target-mips: Add ASE DSP multiply instructionsJia Liu2012-10-311-0/+485
* target-mips: Add ASE DSP GPR-based shift instructionsJia Liu2012-10-311-0/+324
* target-mips: Add ASE DSP arithmetic instructionsJia Liu2012-10-311-3/+792
* target-mips: Add ASE DSP load instructionsJia Liu2012-10-311-0/+88
* target-mips: Add ASE DSP branch instructionsJia Liu2012-10-311-0/+36
* Use correct acc value to index cpu_HI/cpu_LO rather than using a fix numberJia Liu2012-10-311-27/+95
* target-mips: Add ASE DSP resources access checkJia Liu2012-10-311-0/+23
* target-mips: Use TCG registers for the FPU.Richard Henderson2012-10-281-42/+54
* Emit debug_insn for CPU_LOG_TB_OP_OPT as well.Richard Henderson2012-09-271-1/+2
* target-mips: Implement Loongson Multimedia InstructionsRichard Henderson2012-09-191-3/+376
* target-mips: Always evaluate debugging macro argumentsRichard Henderson2012-09-191-14/+17
* target-mips: Fix MIPS_DEBUG.Richard Henderson2012-09-191-36/+38
* target-mips: Set opn in gen_ldst_multiple.Richard Henderson2012-09-191-0/+6
* target-mips: switch to AREG0 free modeBlue Swirl2012-09-151-368/+386
* MIPS/user: Fix reset CPU state initializationMaciej W. Rozycki2012-09-081-13/+3
* target-mips: allow microMIPS SWP and SDP to have RD equal to BASEEric Johnson2012-08-271-1/+9
* target-mips: add privilege level check to several Cop0 instructionsEric Johnson2012-08-271-0/+9
* mips-linux-user: Always support rdhwr.Richard Henderson2012-08-271-0/+4
* target-mips: Streamline indexed cp1 memory addressing.Richard Henderson2012-08-271-2/+1
* Fix order of CVT.PS.S operandsRichard Sandiford2012-08-271-1/+1
* Fix operands of RECIP2.S and RECIP2.PSRichard Sandiford2012-08-271-2/+2
* target-mips: Enable access to required RDHWR hardware registersMeador Inge2012-08-231-2/+3
* MIPS: Correct FCR0 initializationNathan Froyd2012-08-091-0/+1
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