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* target-mips: fix conditional moves off fp condition codesNathan Froyd2009-08-251-5/+5
* Update to a hopefully more future proof FSF addressBlue Swirl2009-07-161-2/+1
* target-mips: remove useless code in gen_st_cond()Aurelien Jarno2009-07-121-1/+0
* Fix MIPS SCPaul Brook2009-07-121-2/+2
* MIPS atomic instructionsPaul Brook2009-07-091-24/+59
* target-mips: fix MADD and MSUB/MSUBU instructionsNathan Froyd2009-07-031-3/+3
* Replace gcc variadic macro extension with C99 versionBlue Swirl2009-05-131-3/+3
* target-mips: proper sign extension for 'SUBU rd, zero, rt'Aurelien Jarno2009-05-041-0/+1
* target-mips: fix comments about SUB/DSUBAurelien Jarno2009-05-041-2/+2
* qemu: introduce qemu_init_vcpu (Marcelo Tosatti)aliguori2009-04-241-0/+1
* Enable access to SYNCI_Step register in usermode emulation.pbrook2009-04-201-0/+2
* Revert "target-mips: fix call to check_*() functions"aurel322009-04-171-24/+12
* target-mips: simplify exception generationaurel322009-04-171-4/+0
* target-mips: fix revision r7126aurel322009-04-161-1/+1
* target-mips: fix call to check_*() functionsaurel322009-04-161-12/+24
* target-mips: optimize gen_flt3_ldst()aurel322009-04-161-4/+4
* target-mips: optimize gen_flt_ldst()aurel322009-04-161-4/+2
* Stop translation after a syscall instruciton.pbrook2009-04-161-0/+1
* target-mips: mark zero register as unused.aurel322009-04-151-0/+1
* target-mips: variable names consistencyaurel322009-04-151-402/+404
* target-mips: fix commits 7040 and 7042aurel322009-04-131-2/+6
* target-mips: fix commit 7046aurel322009-04-121-2/+2
* target-mips: don't map zero register as a TCG globalaurel322009-04-111-1/+1
* target-mips: optimize gen_ldst()aurel322009-04-111-22/+64
* target-mips: optimize gen_arith_imm()aurel322009-04-111-106/+161
* target-mips: fix commit r7076aurel322009-04-101-2/+1
* target-mips: optimize gen_movcf_d()aurel322009-04-101-1/+1
* target-mips: optimize a few tcg_temp_free()aurel322009-04-101-3/+3
* target-mips: optimize gen_farith()aurel322009-04-081-56/+47
* target-mips: optimize gen_flt3_arith()aurel322009-04-081-18/+16
* target-mips: optimize gen_flt3_ldst()aurel322009-04-081-9/+4
* target-mips: optimize gen_arith()aurel322009-04-081-158/+290
* target-mips: optimize decode_opc()aurel322009-04-081-13/+17
* target-mips: optimize gen_cp1()aurel322009-04-081-15/+5
* target-mips: optimize gen_cp0()aurel322009-04-081-27/+5
* Add new command line option -singlestep for tcg single stepping.aurel322009-04-051-4/+3
* target-mips: optimize gen_movcf_*()aurel322009-03-291-51/+23
* target-mips: optimize gen_movci()aurel322009-03-291-15/+17
* target-mips: optimize gen_compute_branch1()aurel322009-03-291-107/+57
* target-mips: don't map FP registers as TCG global variablesaurel322009-03-291-35/+30
* target-mips: fix divu instructionaurel322009-03-291-0/+2
* target-mips: optimize write to env->hflagsaurel322009-03-291-14/+7
* target-mips: optimize gen_muldiv()aurel322009-03-291-123/+115
* target-mips: optimize gen_HILO()aurel322009-03-291-4/+0
* target-mips: optimize gen_trap()aurel322009-03-291-26/+12
* target-mips: optimize gen_compute_branch()aurel322009-03-291-48/+43
* target-mips: don't mix result and arguments in gen_op_*aurel322009-03-291-54/+54
* target-mips: gen_bshfl()aurel322009-03-291-29/+45
* target-mips: optimize gen_mul_vr54xx()aurel322009-03-291-2/+2
* target-mips: optimize gen_cl()aurel322009-03-291-15/+11
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